commit 407fc253a7d9a1b81ff196b2ad35401994ff08a4 Author: sdt-haejun Date: Wed Oct 4 16:29:08 2023 +0900 test diff --git a/meta-erlang b/meta-erlang new file mode 160000 index 0000000..0f1df4c --- /dev/null +++ b/meta-erlang @@ -0,0 +1 @@ +Subproject commit 0f1df4c2c2488337faf1763ff45d5efdb7c45389 diff --git a/meta-java b/meta-java new file mode 160000 index 0000000..95d56a6 --- /dev/null +++ b/meta-java @@ -0,0 +1 @@ +Subproject commit 95d56a63cdbf1ed9db99a1f02075568fd45a668b diff --git a/meta-jupyter b/meta-jupyter new file mode 160000 index 0000000..375b6d5 --- /dev/null +++ b/meta-jupyter @@ -0,0 +1 @@ +Subproject commit 375b6d568db13ce273844a0acd97c27b4362bdae diff --git a/meta-openembedded b/meta-openembedded new file mode 160000 index 0000000..b5f510e --- /dev/null +++ b/meta-openembedded @@ -0,0 +1 @@ +Subproject commit b5f510e48080b6dc710ff4800feb90ef679c5456 diff --git a/meta-qt5 b/meta-qt5 new file mode 160000 index 0000000..ac7514e --- /dev/null +++ b/meta-qt5 @@ -0,0 +1 @@ +Subproject commit ac7514e2bc295c97faa86d24e8823829257adbb8 diff --git a/meta-scikit-learn b/meta-scikit-learn new file mode 160000 index 0000000..b5ee092 --- /dev/null +++ b/meta-scikit-learn @@ -0,0 +1 @@ +Subproject commit b5ee092c410efa4a20931b5f0d1450a5cf872f58 diff --git a/meta-scipy b/meta-scipy new file mode 160000 index 0000000..4384f87 --- /dev/null +++ b/meta-scipy @@ -0,0 +1 @@ +Subproject commit 4384f87b1908e9a856aedf0b75d48b77408c1463 diff --git a/meta-security b/meta-security new file mode 160000 index 0000000..6466c6f --- /dev/null +++ b/meta-security @@ -0,0 +1 @@ +Subproject commit 6466c6fb02f36f459b06d434484df26e083f3489 diff --git a/meta-st/meta-st-openstlinux b/meta-st/meta-st-openstlinux new file mode 160000 index 0000000..5465ed3 --- /dev/null +++ b/meta-st/meta-st-openstlinux @@ -0,0 +1 @@ +Subproject commit 5465ed3781355776cb46d2cc45884b1ccc1011cd diff --git a/meta-st/meta-st-stm32mp b/meta-st/meta-st-stm32mp new file mode 160000 index 0000000..7a1ab80 --- /dev/null +++ b/meta-st/meta-st-stm32mp @@ -0,0 +1 @@ +Subproject commit 7a1ab80ccb655e9cd28c9ea8a4a83fca48c48b11 diff --git a/meta-st/meta-st-stm32mp-addons b/meta-st/meta-st-stm32mp-addons new file mode 160000 index 0000000..2b992cd --- /dev/null +++ b/meta-st/meta-st-stm32mp-addons @@ -0,0 +1 @@ +Subproject commit 2b992cde26a4df9da34d8baee8491b3d9bc8f109 diff --git a/meta-st/meta-st-stm32mpu-hce/CONTRIBUTING.md b/meta-st/meta-st-stm32mpu-hce/CONTRIBUTING.md new file mode 100644 index 0000000..3d1bacd --- /dev/null +++ b/meta-st/meta-st-stm32mpu-hce/CONTRIBUTING.md @@ -0,0 +1,30 @@ +# Contributing guide + +This document serves as a checklist before contributing to this repository. It includes links to read up on if topics are unclear to you. + +This guide mainly focuses on the proper use of Git. + +## 1. Issues + +STM32MPU projects do not activate "Github issues" feature for the time being. If you need to report an issue or question about this project deliverables, you can report them using [ ST Support Center ](https://my.st.com/ols#/ols/newrequest) or [ ST Community MPU Forum ](https://community.st.com/s/topic/0TO0X0000003u2AWAQ/stm32-mpus). + +## 2. Pull Requests + +STMicrolectronics is happy to receive contributions from the community, based on an initial Contributor License Agreement (CLA) procedure. + +* If you are an individual writing original source code and you are sure **you own the intellectual property**, then you need to sign an Individual CLA (https://cla.st.com). +* If you work for a company that wants also to allow you to contribute with your work, your company needs to provide a Corporate CLA (https://cla.st.com) mentioning your GitHub account name. +* If you are not sure that a CLA (Individual or Corporate) has been signed for your GitHub account you can check here (https://cla.st.com). + +Please note that: +* The Corporate CLA will always take precedence over the Individual CLA. +* One CLA submission is sufficient, for any project proposed by STMicroelectronics. + +__How to proceed__ + +* We recommend to fork the project in your GitHub account to further develop your contribution. Please use the latest commit version. +* Please, submit one Pull Request for one new feature or proposal. This will ease the analysis and final merge if accepted. + +__Note__ + +Merge will not be done directly in GitHub but it will need first to follow internal integration process before public deliver in a standard release. The Pull request will stay open until it is merged and delivered. diff --git a/meta-st/meta-st-stm32mpu-hce/License.md b/meta-st/meta-st-stm32mpu-hce/License.md new file mode 100644 index 0000000..07c1aff --- /dev/null +++ b/meta-st/meta-st-stm32mpu-hce/License.md @@ -0,0 +1 @@ +http://wiki.st.com/stm32mpu/index.php/OpenSTLinux_licenses diff --git a/meta-st/meta-st-stm32mpu-hce/README.md b/meta-st/meta-st-stm32mpu-hce/README.md new file mode 100644 index 0000000..839ecd0 --- /dev/null +++ b/meta-st/meta-st-stm32mpu-hce/README.md @@ -0,0 +1,310 @@ +## meta-st-stm32mpu-hce +## OpenEmbedded meta layer to install a AWS greengrass application. + +ref : https://aws.amazon.com/fr/greengrass/ + +This document describe the process to add the "AWS greengrass" application in the openSTlinux distribution, and how to configure the target to execute the AWS greengrass certification included the Hardware Security Integration test group.
+The Hardware Security Module used is the STM4RasPI expansion board (component TPM2 ST33TPHF20SPI). + +Notes : +1. This process has been tested with the STM32MP1 OpenSTLinux distribution MMDV-v2.0.0 (openstlinux-5.4-dunfell-mp1-20-06-24). +2. This process has been tested with following software release : +- meta-java: "3b65eea96eddde97169ca5e00be01a9dbd257786" +- meta-virtualization: "ff997b6b3ba800978546098ab3cdaa113b6695e1" +- meta-security: "c74cc97641fd93e0e7a4383255e9a0ab3deaf9d7" +3. The Greengrass application is delivered by Amazon as binaries for a RASPBIAN distribution. +4. The AWS IoT Greengrass version installed is v1.11.0, AWS IoT Device Tester version used for AWS certification is IDT v3.2.0 +5. The target is configured to Support the Greengrass Over-the-Air Updates (OTA) + +## Process for installation : +#### Install the openSTlinux distribution yocto environment on your Host. +ref : [STM32MP1 Distribution Package - OpenSTLinux distribution](https://wiki.st.com/stm32mpu/wiki/STM32MP1_Distribution_Package_-_OpenSTLinux_distribution) + +#### Clone following git repository into [your STM32MP1 Distribution path]/layers/meta-st/ + > **PC $>** cd [your STM32MP1 Distribution path]/layers/meta-st
+ > **PC $>** git clone https://github.com/SigmaDeltaTechnologiesInc/meta-st-stm32mpu-hce
+ > **PC $>** cd meta-st-stm32mpu-hce
+ > **PC $>** git checkout remotes/origin/dunfell + +#### Add TPM2 recipes + > **PC $>** cd [your STM32MP1 Distribution path]/layers
+ > **PC $>** git clone git://git.yoctoproject.org/meta-security
+ > **PC $>** cd meta-security
+ > **PC $>** git checkout remotes/origin/dunfell
+ +#### Setup the build environment +Executes the command, on the host : + > **PC $>** cd [your STM32MP1 Distribution path]
+ > **PC $>** DISTRO=openstlinux-weston MACHINE=stm32mp1-hce source layers/meta-st/scripts/envsetup.sh + +#### Add Virtualization (docker) in OpenSTLinux distribution + > **PC $>** cd [your STM32MP1 Distribution path]/layers
+ > **PC $>** git clone git://git.yoctoproject.org/meta-virtualization
+ > **PC $>** cd meta-virtualization
+ > **PC $>** git checkout remotes/origin/dunfell
+ > **PC $>** cd [your STM32MP1 Distribution path]/build-openstlinuxweston-stm32mp1-hce
+ > **PC $>** bitbake-layers add-layer [your STM32MP1 Distribution path]/layers/meta-virtualization + + +Apply the following update in the file _[your STM32MP1 Distribution path]/layers/meta-st/meta-st-openstlinux/conf/distro/openstlinux-weston.conf_ + +``` + DISTRO_FEATURES_append = " virtualization " +``` + +#### Add JAVA JDK in OpenSTLinux distribution + > **PC $>** cd [your STM32MP1 Distribution path]/layers
+ > **PC $>** git clone git://git.yoctoproject.org/meta-java
+ > **PC $>** cd meta-java
+ > **PC $>** git checkout remotes/origin/dunfell
+ > **PC $>** cd [your STM32MP1 Distribution path]/build-openstlinuxweston-stm32mp1-hce
+ > **PC $>** bitbake-layers add-layer [your STM32MP1 Distribution path]/layers/meta-java + +Apply the following update in the file _[your STM32MP1 Distribution path]/build-openstlinuxweston-stm32mp1-hce/conf/local.conf_ + +``` +# Possible provider: cacao-initial-native and jamvm-initial-native +PREFERRED_PROVIDER_virtual/java-initial-native = "cacao-initial-native" + +# Possible provider: cacao-native and jamvm-native +PREFERRED_PROVIDER_virtual/java-native = "jamvm-native" + +# Optional since there is only one provider for now +PREFERRED_PROVIDER_virtual/javac-native = "ecj-bootstrap-native" +``` + + +#### Increase the ROOFS partition size +Update the file _[your STM32MP1 Distribution path]/layers/meta-st/meta-st-stm32mp/conf/machine/include/st-machine-common-stm32mp.inc_ + +``` +IMAGE_ROOTFS_MAXSIZE = "2097152" +``` + +#### Increase the BOOFS partition size +Update the file _[your STM32MP1 Distribution path]/layers/meta-st/meta-st-stm32mp/conf/machine/include/st-machine-common-stm32mp.inc_ + +``` +BOOTFS_PARTITION_SIZE = "512000" +``` + +#### Enable TPM build +Apply the following update in the file _[your STM32MP1 Distribution path]/layers/meta-st/meta-st-openstlinux/conf/distro/include/openstlinux.inc_ + +``` +DISTRO_FEATURES_append = " tpm2 " +``` + +#### Add AWS + > **PC $>** cd [your STM32MP1 Distribution path]/layers
+ > **PC $>** git clone https://github.com/aws/meta-aws
+ > **PC $>** cd meta-aws
+ > **PC $>** git checkout remotes/origin/dunfell
+ > **PC $>** cd [your STM32MP1 Distribution path]/build-openstlinuxweston-stm32mp1-hce
+ > **PC $>** bitbake-layers add-layer [your STM32MP1 Distribution path]/layers/meta-aws + + +### Add meta-scipy Layer + > **PC $>** cd [your STM32MP1 Distribution path]/layers
+ > **PC $>** git clone https://github.com/gpanders/meta-scipy
+ > **PC $>** cd meta-scipy
+ > **PC $>** git checkout remotes/origin/dunfell
+ > **PC $>** cd [your STM32MP1 Distribution path]/build-openstlinuxweston-stm32mp1-hce
+ > **PC $>** bitbake-layers add-layer [your STM32MP1 Distribution path]/layers/meta-scipy + +### Add meta-scikit-learn Layer + > **PC $>** cd [your STM32MP1 Distribution path]/layers
+ > **PC $>** git clone https://github.com/tuxable-ltd/meta-scikit-learn
+ > **PC $>** cd meta-scikit-learn
+ > **PC $>** git checkout remotes/origin/dunfell
+ > **PC $>** cd [your STM32MP1 Distribution path]/build-openstlinuxweston-stm32mp1-hce
+ > **PC $>** bitbake-layers add-layer [your STM32MP1 Distribution path]/layers/meta-scikit-learn + + + +#### Build the image +In the folder _[your STM32MP1 Distribution path]/build-openstlinuxweston-stm32mp1-hce_ + +Executes the command : + > **PC $>** bitbake st-image-hce + +#### Flash the emmc +The tsv file _flashlayout_st-image-hce/trusted/FlashLayout_emmc_stm32mp157c-hce-mx-trusted.tsv_ is located in
+_[your STM32MP1 Distribution path]/build-openstlinuxweston-stm32mp1-hce/tmp-glibc/deploy/images/stm32mp1-hce/flashlayout_st-image-hce_ + +ref : [STM32CubeProgrammer](https://wiki.st.com/stm32mpu/wiki/STM32CubeProgrammer) + +#### Run the scripts for some extra configuration on the target (to execute only one time after the first boot) +Executes the commands, on the target : + +``` +Board $> source /greengrass/tpm_update.sh + +Board $> source /greengrass/aws_certif_update.sh +``` + +#### TPM2 token intialisation +Note : keep the PINs (123456) and PKCS11 STORE folder (usr/local/pkcs11_tpm), scripts and greengrass config files examples use these values. +Executes the commands, on the target : + +``` +Board $> cd /tools + +Board $> ./tpm2_ptool.py init --primary-auth=123456 --path=$TPM2_PKCS11_STORE + +Board $> ./tpm2_ptool.py addtoken --pid=1 --sopin=123456 --userpin=123456 --label=greengrass --path $TPM2_PKCS11_STORE + +Board $> ./tpm2_ptool.py addkey --algorithm=rsa2048 --label="greengrass" --userpin=123456 --key-label=greenkey --path=$TPM2_PKCS11_STORE + +``` +#### OPTIONAL : Verifications with pkcs11-tool + +Executes this command on the target to verify the token created. + +``` +Board $> pkcs11-tool --module /usr/lib/libtpm2_pkcs11.so.0 -L +``` + +Output : + +

+Available slots:
+   Slot 0 (0x1): greengrass STMicro
+     token label        : greengrass
+     token manufacturer : STMicro
+     token model        :
+    token flags        : login required, rng, token initialized, PIN initialized
+     hardware version   : 1.38
+     firmware version   : 74.8
+     serial num         : 0000000000000000
+     pin min/max        : 5/128
+
+ + +**AT THIS STEP, THE CONFIGURATION OF THE BOARD IS COMPLETED TO BE USED WITH THE AWS IoT Device Tester.** + +## Process to execute the AWS Greengrass certification testing +A) Go to the Amazon site to [AWS IoT Device Tester for AWS IoT Greengrass Versions](https://docs.aws.amazon.com/greengrass/latest/developerguide/dev-test-versions.html) + +Install the AWS IoT Device Tester. + +B) Configure your ssh connection (ssh keys) + +Go to the Amazon site to [Configure Your Host Computer to Access Your Device Under Test](https://docs.aws.amazon.com/greengrass/latest/developerguide/device-config-setup.html#configure-host) + +C) Configure the IDT + +Example of of the config folder install for Windows. + +>c:\devicetester_greengrass_win\devicetester_greengrass_win\configs\ + +See the Amazon site [Setting Configuration to Run the AWS IoT Greengrass Qualification Suite](https://docs.aws.amazon.com/greengrass/latest/developerguide/set-config.html) + +There is a configuration file example installed on your Host : + +> /[your STM32MP1 Distribution path]/layers/meta-st/meta-st-demo-aws/recipes-aws/greengrasstests/greengrasstests/device-hsm.json + +Note : With this example the certification tests are performed in Root. + +D) Execute the tests, go to the Amazon site to [Running Tests](https://docs.aws.amazon.com/greengrass/latest/developerguide/run-tests.html) + +### Process to to create a Certificat Signature Request using the hardware-protected private key + +1) Update **openssl** tool configuration to use module tpm2_pkcs11 + +add the following lines in /etc/ssl/openssl.cnf at the beginning of the file (after "HOME = .): +

+openssl_conf = openssl_init
+[openssl_init]
+engines=engine_section
+[engine_section]
+pkcs11 = pkcs11_section
+[pkcs11_section]
+engine_id = pkcs11
+dynamic_path = /usr/lib/engines-1.1/pkcs11.so
+MODULE_PATH = /usr/lib/libtpm2_pkcs11.so.0
+init = 0
+
+ +2) How to create a CSR "Certificat Signature Request" with **openssl** +Executes the command, on target : +``` +Board $> openssl req -engine pkcs11 -new -key "pkcs11:token=greengrass;object=greenkey;type=private;pin-value=123456" -keyform engine -out /usr/local/req.csr +``` + +This CSR "**/usr/local/req.csr**" is used to create clients certificats on the AWS amazon Cloud to store on the board.
+There is a greengrass configuration file example to update with your AWS account parameter and certificats created, on the target : **/greengrass/config/config\_secu\_example.json**
+You need also to download the root CA on Amazon site and stored it on the target **greengrass/certs/root.ca.pem**. + +3) Connection to Amazon cloud + +Before starting the greengrass core on the target you need to set the **TPM2\_PKCS11\_STORE** environment variable. + +Executes the command on the target : +``` + Board $> export TPM2_PKCS11_STORE=/usr/local/pkcs11_tpm +``` + +### In case of trouble to reinit all the TPM/PKCS11 layers + +How to reset the TPM and PKCS11 store : + +Executes the commands, on the target: +``` +Board $> cd /usr/bin +Board $> ./tpm2_clear -Q +Board $> rm /usr/local/pkcs11_tpm/* +``` + +#### Error debug +``` +WARNING: You have included the meta-virtualization layer, but 'virtualization' has not been enabled in your DISTRO_FEATURES. Some bbappend files may not take effect. See the meta-virtualization README for details on enabling virtualization support. +ERROR: ParseError at /home/mirika-rnd/Work/STM32MP15-Ecosystem-v2.0.0-Mando/Distribution-Package//openstlinux-5.4-dunfell-mp1-20-06-24/layers/meta-virtualization/recipes-extended/libvirt/libvirt-python.inc:1: Could not inherit file classes/python3targetconfig.bbclass +``` + +remove python3targetconfig 1 line in libvirt-python.inc + + +``` +ERROR: ParseError at /home/mirika-rnd/Work/STM32MP15-Ecosystem-v2.0.0-Mando/Distribution-Package/openstlinux-5.4-dunfell-mp1-20-06-24/layers/meta-security/recipes-mac/AppArmor/apparmor_2.13.6.bb:37: Could not inherit file classes/python3targetconfig.bbclass +``` + +Remove python3targetconfig 37 line in apparmor_2.13.6.bb + + +``` +ERROR: Nothing RPROVIDES 'openjdk-8' (but /home/mirika-rnd/Work/STM32MP15-Ecosystem-v2.0.0-Mando/Distribution-Package/openstlinux-5.4-dunfell-mp1-20-06-24/layers/meta-st/meta-st-stm32mpu-hce/recipes-st/images/st-image-aws-ec21.bb RDEPENDS on or otherwise requires it) +NOTE: Runtime target 'openjdk-8' is unbuildable, removing... +Missing or unbuildable dependency chain was: ['openjdk-8'] +``` +sudo apt-get install openjdk-8-jdk + +``` +ERROR: Nothing PROVIDES 'libgfortran' (but /home/builder/Workspace/Distribution-Package/openstlinux-5.4-dunfell-mp1-20-06-24/layers/meta-openembedded/meta-oe/recipes-devtools/lapack/lapack_3.9.0.bb DEPENDS on or otherwise requires it) +libgfortran was skipped: libgfortran needs fortran support to be enabled in the compiler +ERROR: Required build target 'python3-scipy' has no buildable providers. +Missing or unbuildable dependency chain was: ['python3-scipy', 'lapack', 'libgfortran'] +``` +sudo apt-get install -y libgfortran-8-dev + + +Added by SDT in local.conf for HCE +``` +# Possible provider: cacao-initial-native and jamvm-initial-native +PREFERRED_PROVIDER_virtual/java-initial-native = "cacao-initial-native" +# Possible provider: cacao-native and jamvm-native +PREFERRED_PROVIDER_virtual/java-native = "jamvm-native" +# Optional since there is only one provider for now +PREFERRED_PROVIDER_virtual/javac-native = "ecj-bootstrap-native" +# ========================================================================= +# SDT cumtomize +IMAGE_INSTALL_append = " python3-pandas python3-numpy python3-can" +IMAGE_INSTALL_append = " python3-scikit-learn python3-scipy " +FORTRAN_forcevariable = ",fortran" +RUNTIMETARGET_append_pn-gcc-runtime = " libquadmath" +HOSTTOOLS += "gfortran" +# ========================================================================= +``` + + +SDT.inc diff --git a/meta-st/meta-st-stm32mpu-hce/conf/eula/LICENCE.broadcom_bcm43xx b/meta-st/meta-st-stm32mpu-hce/conf/eula/LICENCE.broadcom_bcm43xx new file mode 100644 index 0000000..ff26fdd --- /dev/null +++ b/meta-st/meta-st-stm32mpu-hce/conf/eula/LICENCE.broadcom_bcm43xx @@ -0,0 +1,65 @@ +SOFTWARE LICENSE AGREEMENT + +The accompanying software in binary code form (“Software”), is licensed to you, +or, if you are accepting on behalf of an entity, the entity and its affiliates +exercising rights hereunder (“Licensee”) subject to the terms of this software +license agreement (“Agreement”), unless Licensee and Broadcom Corporation +(“Broadcom”) execute a separate written software license agreement governing +use of the Software. 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Portions of the Software may be licensed under +free and/or open source licenses such as the GNU General Public License +("FOSS"). FOSS is subject to the applicable license agreement and not this +Agreement. If you are entitled to receive the source code from Cypress for any +FOSS included with the Software, either the source code will be included with +the Software or you may obtain the source code at no charge from +. The applicable license terms will +accompany each source code package. To review the license terms applicable to +any FOSS for which Cypress is not required to provide you with source code, +please see the Software's installation directory on your computer. + +Proprietary Rights. The Software, including all intellectual property rights +therein, is and will remain the sole and exclusive property of Cypress or its +suppliers. Except as otherwise expressly provided in this Agreement, you may +not: (i) modify, adapt, or create derivative works based upon the Software; +(ii) copy the Software; (iii) except and only to the extent explicitly +permitted by applicable law despite this limitation, decompile, translate, +reverse engineer, disassemble or otherwise reduce the Software to +human-readable form; or (iv) use the Software other than for the Purpose. + +No Support. Cypress may, but is not required to, provide technical support for +the Software. + +Term and Termination. This Agreement is effective until terminated, and either +party may terminate this Agreement at any time with or without cause. Your +license rights under this Agreement will terminate immediately without notice +from Cypress if you fail to comply with any provision of this Agreement. Upon +termination, you must destroy all copies of Software in your possession or +control. Termination of this Agreement will not affect any licenses validly +granted as of the termination date to any end users of the Software. The +following paragraphs shall survive any termination of this Agreement: "Free and +Open Source Software," "Proprietary Rights," "Compliance With Law," +"Disclaimer," "Limitation of Liability," and "General." + +Compliance With Law. Each party agrees to comply with all applicable laws, +rules and regulations in connection with its activities under this Agreement. +Without limiting the foregoing, the Software may be subject to export control +laws and regulations of the United States and other countries. You agree to +comply strictly with all such laws and regulations and acknowledge that you +have the responsibility to obtain licenses to export, re-export, or import +the Software. + +Disclaimer. TO THE MAXIMUM EXTENT PERMITTED BY APPLICABLE LAW, CYPRESS MAKES +NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THE SOFTWARE, +INCLUDING, BUT NOT LIMITED TO, INFRINGEMENT AND THE IMPLIED WARRANTIES OF +MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the +right to make changes to the Software without notice. Cypress does not assume +any liability arising out of the application or use of Software or any +product or circuit described in the Software. Cypress does not authorize its +products for use as critical components in life-support systems where a +malfunction or failure may reasonably be expected to result in significant +injury to the user. The inclusion of Cypress' product in a life-support +system or application implies that the manufacturer of such system or +application assumes all risk of such use and in doing so indemnifies Cypress +against all charges. + +Limitation of Liability. IN NO EVENT WILL CYPRESS OR ITS SUPPLIERS, +RESELLERS, OR DISTRIBUTORS BE LIABLE FOR ANY LOST REVENUE, PROFIT, OR DATA, +OR FOR SPECIAL, INDIRECT, CONSEQUENTIAL, INCIDENTAL, OR PUNITIVE DAMAGES +HOWEVER CAUSED AND REGARDLESS OF THE THEORY OF LIABILITY, ARISING OUT OF THE +USE OF OR INABILITY TO USE THE SOFTWARE EVEN IF CYPRESS OR ITS SUPPLIERS, +RESELLERS, OR DISTRIBUTORS HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH +DAMAGES. IN NO EVENT SHALL CYPRESS' OR ITS SUPPLIERS' RESELLERS', OR +DISTRIBUTORS' TOTAL LIABILITY TO YOU, WHETHER IN CONTRACT, TORT (INCLUDING +NEGLIGENCE), OR OTHERWISE, EXCEED THE PRICE PAID BY YOU FOR THE SOFTWARE. +THE FOREGOING LIMITATIONS SHALL APPLY EVEN IF THE ABOVE-STATED WARRANTY FAILS +OF ITS ESSENTIAL PURPOSE. BECAUSE SOME STATES OR JURISDICTIONS DO NOT ALLOW +LIMITATION OR EXCLUSION OF CONSEQUENTIAL OR INCIDENTAL DAMAGES, THE ABOVE +LIMITATION MAY NOT APPLY TO YOU. + +Restricted Rights. The Software under this Agreement is commercial computer +software as that term is described in 48 C.F.R. 252.227-7014(a)(1). If +acquired by or on behalf of a civilian agency, the U.S. Government acquires +this commercial computer software and/or commercial computer software +documentation subject to the terms of this Agreement as specified in 48 +C.F.R. 12.212 (Computer Software) and 12.211 (Technical Data) of the Federal +Acquisition Regulations ("FAR") and its successors. If acquired by or on +behalf of any agency within the Department of Defense ("DOD"), the U.S. +Government acquires this commercial computer software and/or commercial +computer software documentation subject to the terms of this Agreement as +specified in 48 C.F.R. 227.7202-3 of the DOD FAR Supplement ("DFAR") and its +successors. + +General. This Agreement will bind and inure to the benefit of each party's +successors and assigns, provided that you may not assign or transfer this +Agreement, in whole or in part, without Cypress' written consent. This +Agreement shall be governed by and construed in accordance with the laws of +the State of California, United States of America, as if performed wholly +within the state and without giving effect to the principles of conflict of +law. The parties consent to personal and exclusive jurisdiction of and venue +in, the state and federal courts within Santa Clara County, California; +provided however, that nothing in this Agreement will limit Cypress' right to +bring legal action in any venue in order to protect or enforce its +intellectual property rights. No failure of either party to exercise or +enforce any of its rights under this Agreement will act as a waiver of such +rights. If any portion hereof is found to be void or unenforceable, the +remaining provisions of this Agreement shall remain in full force and +effect. This Agreement is the complete and exclusive agreement between the +parties with respect to the subject matter hereof, superseding and replacing +any and all prior agreements, communications, and understandings (both +written and oral) regarding such subject matter. Any notice to Cypress will +be deemed effective when actually received and must be sent to Cypress +Semiconductor Corporation, ATTN: Chief Legal Officer, 198 Champion Court, San +Jose, CA 95134 USA. diff --git a/meta-st/meta-st-stm32mpu-hce/conf/eula/ST_EULA_SLA b/meta-st/meta-st-stm32mpu-hce/conf/eula/ST_EULA_SLA new file mode 100644 index 0000000..5fbc604 --- /dev/null +++ b/meta-st/meta-st-stm32mpu-hce/conf/eula/ST_EULA_SLA @@ -0,0 +1,97 @@ +SLA0048 Rev4/March 2018 + +BY INSTALLING COPYING, DOWNLOADING, ACCESSING OR OTHERWISE USING THIS SOFTWARE PACKAGE OR ANY PART THEREOF (AND THE RELATED DOCUMENTATION) FROM STMICROELECTRONICS INTERNATIONAL N.V, SWISS BRANCH AND/OR ITS AFFILIATED COMPANIES (STMICROELECTRONICS), THE RECIPIENT, ON BEHALF OF HIMSELF OR HERSELF, OR ON BEHALF OF ANY ENTITY BY WHICH SUCH RECIPIENT IS EMPLOYED AND/OR ENGAGED AGREES TO BE BOUND BY THIS SOFTWARE PACKAGE LICENSE AGREEMENT. + +Under STMicroelectronics’ intellectual property rights and subject to applicable licensing terms for any third-party software incorporated in this software package and applicable Open Source Terms (as defined here below), the redistribution, reproduction and use in source and binary forms of the software package or any part thereof, with or without modification, are permitted provided that the following conditions are met: +1. Redistribution of source code (modified or not) must retain any copyright notice, this list of conditions and the following disclaimer. +2. Redistributions in binary form, except as embedded into microcontroller or microprocessor device manufactured by or for STMicroelectronics or a software update for such device, must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. +3. Neither the name of STMicroelectronics nor the names of other contributors to this software package may be used to endorse or promote products derived from this software package or part thereof without specific written permission. +4. This software package or any part thereof, including modifications and/or derivative works of this software package, must be used and execute solely and exclusively on or in combination with a microcontroller or a microprocessor devices manufactured by or for STMicroelectronics. +5. No use, reproduction or redistribution of this software package partially or totally may be done in any manner that would subject this software package to any Open Source Terms (as defined below). +6. Some portion of the software package may contain software subject to Open Source Terms (as defined below) applicable for each such portion (“Open Source Software”), as further specified in the software package. Such Open Source Software is supplied under the applicable Open Source Terms and is not subject to the terms and conditions of license hereunder. “Open Source Terms” shall mean any open source license which requires as part of distribution of software that the source code of such software is distributed therewith or otherwise made available, or open source license that substantially complies with the Open Source definition specified at www.opensource.org and any other comparable open source license such as for example GNU General Public License (GPL), Eclipse Public License (EPL), Apache Software License, BSD license and MIT license. +7. This software package may also include third party software as expressly specified in the software package subject to specific license terms from such third parties. Such third party software is supplied under such specific license terms and is not subject to the terms and conditions of license hereunder. By installing copying, downloading, accessing or otherwise using this software package, the recipient agrees to be bound by such license terms with regard to such third party software. +8. STMicroelectronics has no obligation to provide any maintenance, support or updates for the software package. +9. The software package is and will remain the exclusive property of STMicroelectronics and its licensors. The recipient will not take any action that jeopardizes STMicroelectronics and its licensors' proprietary rights or acquire any rights in the software package, except the limited rights specified hereunder. +10. The recipient shall comply with all applicable laws and regulations affecting the use of the software package or any part thereof including any applicable export control law or regulation. +11. Redistribution and use of this software package partially or any part thereof other than as permitted under this license is void and will automatically terminate your rights under this license. + +THIS SOFTWARE PACKAGE IS PROVIDED BY STMICROELECTRONICS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS, IMPLIED OR STATUTORY WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS ARE DISCLAIMED TO THE FULLEST EXTENT PERMITTED BY LAW. IN NO EVENT SHALL STMICROELECTRONICS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE PACKAGE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +EXCEPT AS EXPRESSLY PERMITTED HEREUNDER AND SUBJECT TO THE APPLICABLE LICENSING TERMS FOR ANY THIRD-PARTY SOFTWARE INCORPORATED IN THE SOFTWARE PACKAGE AND OPEN SOURCE TERMS AS APPLICABLE, NO LICENSE OR OTHER RIGHTS, WHETHER EXPRESS OR IMPLIED, ARE GRANTED UNDER ANY PATENT OR OTHER INTELLECTUAL PROPERTY RIGHTS OF STMICROELECTRONICS OR ANY THIRD PARTY. + +############################################################################### + +Vivante End User Software License Terms + +The following are the terms to be agreed to by end users of Vivante Software licensed herein: + +Copyright 2003-2017 Vivante Corporation, all rights reserved. + +Use, reproduction and redistribution of this software in binary form, without modification and solely for use in conjunction with STMicroelectronics semiconductor chips with the Linux operating system environment that contain Vivante Corporation’s technology, are permitted provided that the following conditions are met: + +* Redistributions must reproduce the above copyright notice, this list of conditions and the following disclaimers in the documentation and/or other materials provided with the distribution. + +* Neither the name nor trademarks of STMicroelectronics International N.V. nor any other STMicroelectronics company (nor Vivante Corporation unless permission is granted separately by Vivante Corporation) may be used to endorse or promote products derived from this software without specific prior written permission. + +* No reverse engineering, decompilation or disassembly of this software is permitted. + +* No use, reproduction or redistribution of this software may be done in any manner that may cause this software to be redistributed as part of the Linux kernel or in any other manner that would subject this software to the terms of the GNU General Public License, the GNU Lesser General Public License, or any other copyleft license. + +DISCLAIMERS: + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER(S) "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT, ARE DISCLAIMED. IN NO EVENT SHALL STMICROELECTRONICS INTERNATIONAL N.V. NOR ANY OTHER STMICROELECTRONICS COMPANY (NOR VIVANTE CORPORATION) BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +THE DELIVERY OF THIS SOFTWARE DOES NOT CONVEY ANY LICENSE, WHETHER EXPRESS OR IMPLIED, TO ANY THIRD-PARTY INTELLECTUAL PROPERTY RIGHTS. + +EXCEPT THE LIMITED RIGHT TO USE, REPRODUCE AND REDISTRIBUTE THIS SOFTWARE IN BINARY FORM, NO LICENSE OR OTHER RIGHTS, WHETHER EXPRESS OR IMPLIED, ARE GRANTED UNDER ANY PATENT OR OTHER INTELLECTUAL PROPERTY RIGHTS OF STMICROELECTRONICS INTERNATIONAL N.V. OR ANY OTHER STMICROELECTRONICS COMPANY (OR VIVANTE CORPORATION). + + +############################################################################### + +### CYPRESS WIRELESS CONNECTIVITY DEVICES +### DRIVER END USER LICENSE AGREEMENT (SOURCE AND BINARY DISTRIBUTION) + +PLEASE READ THIS END USER LICENSE AGREEMENT ("Agreement") CAREFULLY BEFORE DOWNLOADING, INSTALLING, OR USING THIS SOFTWARE, ANY ACCOMPANYING DOCUMENTATION, OR ANY UPDATES PROVIDED BY CYPRESS ("Software"). BY DOWNLOADING, INSTALLING, OR USING THE SOFTWARE, YOU ARE AGREEING TO BE BOUND BY THIS AGREEMENT. IF YOU DO NOT AGREE TO ALL OF THE TERMS OF THIS AGREEMENT, PROMPTLY RETURN AND DO NOT USE THE SOFTWARE. IF YOU HAVE PURCHASED THE SOFTWARE, YOUR RIGHT TO RETURN THE SOFTWARE EXPIRES 30 DAYS AFTER YOUR PURCHASE AND APPLIES ONLY TO THE ORIGINAL PURCHASER. + +Software Provided in Binary Code Form. This paragraph applies to any Software provided in binary code form. Subject to the terms and conditions of this Agreement, Cypress Semiconductor Corporation ("Cypress") grants you a non-exclusive, non-transferable license under its copyright rights in the Software to reproduce and distribute the Software in object code form only, solely for use in connection with Cypress integrated circuit products ("Purpose"). + +Software Provided in Source Code Form. This paragraph applies to any Software provided in source code form ("Cypress Source Code"). Subject to the terms and conditions of this Agreement, Cypress grants you a non-exclusive, non-transferable license under its copyright rights in the Cypress Source Code to reproduce, modify, compile, and distribute the Cypress Source Code (whether in source code form or as compiled into binary code form) solely for the Purpose. Cypress retains ownership of the Cypress Source Code and any compiled version thereof. Subject to Cypress' ownership of the underlying Cypress Source Code, you retain ownership of any modifications you make to the Cypress Source Code. You agree not to remove any Cypress copyright or other notices from the Cypress Source Code and any modifications thereof. Any reproduction, modification, translation, compilation, or representation of the Cypress Source Code except as permitted in this paragraph is prohibited without the express written permission of Cypress. + +Free and Open Source Software. Portions of the Software may be licensed under free and/or open source licenses such as the GNU General Public License ("FOSS"). FOSS is subject to the applicable license agreement and not this Agreement. If you are entitled to receive the source code from Cypress for any FOSS included with the Software, either the source code will be included with the Software or you may obtain the source code at no charge from . The applicable license terms will accompany each source code package. To review the license terms applicable to any FOSS for which Cypress is not required to provide you with source code, please see the Software's installation directory on your computer. + +Proprietary Rights. The Software, including all intellectual property rights therein, is and will remain the sole and exclusive property of Cypress or its suppliers. Except as otherwise expressly provided in this Agreement, you may not: (i) modify, adapt, or create derivative works based upon the Software; (ii) copy the Software; (iii) except and only to the extent explicitly permitted by applicable law despite this limitation, decompile, translate, reverse engineer, disassemble or otherwise reduce the Software to human-readable form; or (iv) use the Software other than for the Purpose. + +No Support. Cypress may, but is not required to, provide technical support for the Software. + +Term and Termination. This Agreement is effective until terminated, and either party may terminate this Agreement at any time with or without cause. Your license rights under this Agreement will terminate immediately without notice from Cypress if you fail to comply with any provision of this Agreement. Upon termination, you must destroy all copies of Software in your possession or control. Termination of this Agreement will not affect any licenses validly granted as of the termination date to any end users of the Software. The following paragraphs shall survive any termination of this Agreement: "Free and Open Source Software," "Proprietary Rights," "Compliance With Law," "Disclaimer," "Limitation of Liability," and "General." + +Compliance With Law. Each party agrees to comply with all applicable laws, rules and regulations in connection with its activities under this Agreement. Without limiting the foregoing, the Software may be subject to export control laws and regulations of the United States and other countries. You agree to comply strictly with all such laws and regulations and acknowledge that you have the responsibility to obtain licenses to export, re-export, or import the Software. + +Disclaimer. TO THE MAXIMUM EXTENT PERMITTED BY APPLICABLE LAW, CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THE SOFTWARE, INCLUDING, BUT NOT LIMITED TO, INFRINGEMENT AND THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes to the Software without notice. Cypress does not assume any liability arising out of the application or use of Software or any product or circuit described in the Software. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress' product in a life-support system or application implies that the manufacturer of such system or application assumes all risk of such use and in doing so indemnifies Cypress against all charges. + +Limitation of Liability. IN NO EVENT WILL CYPRESS OR ITS SUPPLIERS, RESELLERS, OR DISTRIBUTORS BE LIABLE FOR ANY LOST REVENUE, PROFIT, OR DATA, OR FOR SPECIAL, INDIRECT, CONSEQUENTIAL, INCIDENTAL, OR PUNITIVE DAMAGES HOWEVER CAUSED AND REGARDLESS OF THE THEORY OF LIABILITY, ARISING OUT OF THE USE OF OR INABILITY TO USE THE SOFTWARE EVEN IF CYPRESS OR ITS SUPPLIERS, RESELLERS, OR DISTRIBUTORS HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. IN NO EVENT SHALL CYPRESS' OR ITS SUPPLIERS' RESELLERS', OR DISTRIBUTORS' TOTAL LIABILITY TO YOU, WHETHER IN CONTRACT, TORT (INCLUDING NEGLIGENCE), OR OTHERWISE, EXCEED THE PRICE PAID BY YOU FOR THE SOFTWARE. THE FOREGOING LIMITATIONS SHALL APPLY EVEN IF THE ABOVE-STATED WARRANTY FAILS OF ITS ESSENTIAL PURPOSE. BECAUSE SOME STATES OR JURISDICTIONS DO NOT ALLOW LIMITATION OR EXCLUSION OF CONSEQUENTIAL OR INCIDENTAL DAMAGES, THE ABOVE LIMITATION MAY NOT APPLY TO YOU. + +Restricted Rights. The Software under this Agreement is commercial computer software as that term is described in 48 C.F.R. 252.227-7014(a)(1). If acquired by or on behalf of a civilian agency, the U.S. Government acquires this commercial computer software and/or commercial computer software documentation subject to the terms of this Agreement as specified in 48 C.F.R. 12.212 (Computer Software) and 12.211 (Technical Data) of the Federal Acquisition Regulations ("FAR") and its successors. If acquired by or on behalf of any agency within the Department of Defense ("DOD"), the U.S. Government acquires this commercial computer software and/or commercial computer software documentation subject to the terms of this Agreement as specified in 48 C.F.R. 227.7202-3 of the DOD FAR Supplement ("DFAR") and its successors. + +General. This Agreement will bind and inure to the benefit of each party's successors and assigns, provided that you may not assign or transfer this Agreement, in whole or in part, without Cypress' written consent. This Agreement shall be governed by and construed in accordance with the laws of the State of California, United States of America, as if performed wholly within the state and without giving effect to the principles of conflict of law. The parties consent to personal and exclusive jurisdiction of and venue in, the state and federal courts within Santa Clara County, California; provided however, that nothing in this Agreement will limit Cypress' right to bring legal action in any venue in order to protect or enforce its intellectual property rights. No failure of either party to exercise or enforce any of its rights under this Agreement will act as a waiver of such rights. If any portion hereof is found to be void or unenforceable, the remaining provisions of this Agreement shall remain in full force and effect. This Agreement is the complete and exclusive agreement between the parties with respect to the subject matter hereof, superseding and replacing any and all prior agreements, communications, and understandings (both written and oral) regarding such subject matter. Any notice to Cypress will be deemed effective when actually received and must be sent to Cypress Semiconductor Corporation, ATTN: Chief Legal Officer, 198 Champion Court, San +Jose, CA 95134 USA. + + +############################################################################### + +BROADCOM BCM43XX + +SOFTWARE LICENSE AGREEMENT + +The accompanying software in binary code form (“Software”), is licensed to you, or, if you are accepting on behalf of an entity, the entity and its affiliates exercising rights hereunder (“Licensee”) subject to the terms of this software license agreement (“Agreement”), unless Licensee and Broadcom Corporation (“Broadcom”) execute a separate written software license agreement governing use of the Software. ANY USE, REPRODUCTION, OR DISTRIBUTION OF THE SOFTWARE CONSTITUTES LICENSEE’S ACCEPTANCE OF THIS AGREEMENT. + +1. License. Subject to the terms and conditions of this Agreement, Broadcom hereby grants to Licensee a limited, non-exclusive, non-transferable, royalty-free license: (i) to use and integrate the Software with any other software; and (ii) to reproduce and distribute the Software complete, unmodified, and as provided by Broadcom, solely for use with Broadcom proprietary integrated circuit product(s) sold by Broadcom with which the Software was designed to be used, or their successors. + +2. Restrictions. Licensee shall distribute Software with a copy of this Agreement. Licensee shall not remove, efface or obscure any copyright or trademark notices from the Software. Reproductions of the Broadcom copyright notice shall be included with each copy of the Software, except where such Software is embedded in a manner not readily accessible to the end user. +Licensee shall not: (i) use, license, sell or otherwise distribute the Software except as provided in this Agreement; (ii) attempt to modify in any way, reverse engineer, decompile or disassemble any portion of the Software; or (iii) use the Software or other material in violation of any applicable law or regulation, including but not limited to any regulatory agency. This Agreement shall automatically terminate upon Licensee’s failure to comply with any of the terms of this Agreement. In such event, Licensee will destroy all copies of the Software and its component parts. + +3. Ownership. The Software is licensed and not sold. Title to and ownership of the Software, including all intellectual property rights thereto, and any portion thereof remain with Broadcom or its licensors. Licensee hereby covenants that it will not assert any claim that the Software created by or for Broadcom infringe any intellectual property right owned or controlled by Licensee. + +4. Disclaimer. THE SOFTWARE IS OFFERED “AS IS,” AND BROADCOM PROVIDES AND GRANTS AND LICENSEE RECEIVES NO SUPPORT AND NO WARRANTIES OF ANY KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR CONDUCT WITH LICENSEE, OR OTHERWISE. +BROADCOM SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A SPECIFIC PURPOSE, OR NONINFRINGEMENT CONCERNING THE SOFTWARE OR ANY UPGRADES TO OR DOCUMENTATION FOR THE SOFTWARE. WITHOUT LIMITATION OF THE ABOVE, BROADCOM GRANTS NO WARRANTY THAT THE SOFTWARE IS ERROR-FREE OR WILL OPERATE WITHOUT INTERRUPTION, AND GRANTS NO WARRANTY REGARDING ITS USE OR THE RESULTS THEREFROM INCLUDING, WITHOUT LIMITATION, ITS CORRECTNESS, ACCURACY, OR RELIABILITY. TO THE MAXIMUM EXTENT PERMITTED BY LAW, IN NO EVENT SHALL BROADCOM OR ANY OF ITS LICENSORS HAVE ANY LIABILITY FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, OR CONSEQUENTIAL DAMAGES, HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER FOR BREACH OF CONTRACT, TORT (INCLUDING NEGLIGENCE) OR OTHERWISE, ARISING OUT OF THIS AGREEMENT OR USE, REPRODUCTION, OR DISTRIBUTION OF THE SOFTWARE, INCLUDING BUT NOT LIMITED TO LOSS OF DATA AND LOSS OF PROFITS, EVEN IF SUCH PARTY HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. THESE LIMITATIONS SHALL APPLY NOTWITHSTANDING ANY FAILURE OF ESSENTIAL PURPOSE OF ANY LIMITED REMEDY. + +5. Export Laws. LICENSEE UNDERSTANDS AND AGREES THAT THE SOFTWARE IS SUBJECT TO UNITED STATES AND OTHER APPLICABLE EXPORT-RELATED LAWS AND REGULATIONS AND THAT LICENSEE MAY NOT EXPORT, RE-EXPORT OR TRANSFER THE SOFTWARE OR ANY DIRECT PRODUCT OF THE SOFTWARE EXCEPT AS PERMITTED UNDER THOSE LAWS. WITHOUT LIMITING THE FOREGOING, EXPORT, RE-EXPORT, OR TRANSFER OF THE SOFTWARE TO CUBA, IRAN, NORTH KOREA, SUDAN, AND SYRIA IS PROHIBITED. diff --git a/meta-st/meta-st-stm32mpu-hce/conf/eula/Vivante_GPU_drivers-End_User_Software_License_Terms.txt b/meta-st/meta-st-stm32mpu-hce/conf/eula/Vivante_GPU_drivers-End_User_Software_License_Terms.txt new file mode 100644 index 0000000..8ae7919 --- /dev/null +++ b/meta-st/meta-st-stm32mpu-hce/conf/eula/Vivante_GPU_drivers-End_User_Software_License_Terms.txt @@ -0,0 +1,23 @@ +Vivante End User Software License Terms + +The following are the terms to be agreed to by end users of Vivante Software licensed herein: + +Copyright 2003-2017 Vivante Corporation, all rights reserved. + +Use, reproduction and redistribution of this software in binary form, without modification and solely for use in conjunction with STMicroelectronics semiconductor chips with the Linux operating system environment that contain Vivante Corporation’s technology, are permitted provided that the following conditions are met: + +* Redistributions must reproduce the above copyright notice, this list of conditions and the following disclaimers in the documentation and/or other materials provided with the distribution. + +* Neither the name nor trademarks of STMicroelectronics International N.V. nor any other STMicroelectronics company (nor Vivante Corporation unless permission is granted separately by Vivante Corporation) may be used to endorse or promote products derived from this software without specific prior written permission. + +* No reverse engineering, decompilation or disassembly of this software is permitted. + +* No use, reproduction or redistribution of this software may be done in any manner that may cause this software to be redistributed as part of the Linux kernel or in any other manner that would subject this software to the terms of the GNU General Public License, the GNU Lesser General Public License, or any other copyleft license. + +DISCLAIMERS: + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER(S) "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT, ARE DISCLAIMED. IN NO EVENT SHALL STMICROELECTRONICS INTERNATIONAL N.V. NOR ANY OTHER STMICROELECTRONICS COMPANY (NOR VIVANTE CORPORATION) BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +THE DELIVERY OF THIS SOFTWARE DOES NOT CONVEY ANY LICENSE, WHETHER EXPRESS OR IMPLIED, TO ANY THIRD-PARTY INTELLECTUAL PROPERTY RIGHTS. + +EXCEPT THE LIMITED RIGHT TO USE, REPRODUCE AND REDISTRIBUTE THIS SOFTWARE IN BINARY FORM, NO LICENSE OR OTHER RIGHTS, WHETHER EXPRESS OR IMPLIED, ARE GRANTED UNDER ANY PATENT OR OTHER INTELLECTUAL PROPERTY RIGHTS OF STMICROELECTRONICS INTERNATIONAL N.V. OR ANY OTHER STMICROELECTRONICS COMPANY (OR VIVANTE CORPORATION). diff --git a/meta-st/meta-st-stm32mpu-hce/conf/eula/en.SLA0048.txt b/meta-st/meta-st-stm32mpu-hce/conf/eula/en.SLA0048.txt new file mode 100644 index 0000000..dc344c2 --- /dev/null +++ b/meta-st/meta-st-stm32mpu-hce/conf/eula/en.SLA0048.txt @@ -0,0 +1,19 @@ +SLA0048 Rev4/March 2018 + +BY INSTALLING COPYING, DOWNLOADING, ACCESSING OR OTHERWISE USING THIS SOFTWARE PACKAGE OR ANY PART THEREOF (AND THE RELATED DOCUMENTATION) FROM STMICROELECTRONICS INTERNATIONAL N.V, SWISS BRANCH AND/OR ITS AFFILIATED COMPANIES (STMICROELECTRONICS), THE RECIPIENT, ON BEHALF OF HIMSELF OR HERSELF, OR ON BEHALF OF ANY ENTITY BY WHICH SUCH RECIPIENT IS EMPLOYED AND/OR ENGAGED AGREES TO BE BOUND BY THIS SOFTWARE PACKAGE LICENSE AGREEMENT. + +Under STMicroelectronics’ intellectual property rights and subject to applicable licensing terms for any third-party software incorporated in this software package and applicable Open Source Terms (as defined here below), the redistribution, reproduction and use in source and binary forms of the software package or any part thereof, with or without modification, are permitted provided that the following conditions are met: +1. Redistribution of source code (modified or not) must retain any copyright notice, this list of conditions and the following disclaimer. +2. Redistributions in binary form, except as embedded into microcontroller or microprocessor device manufactured by or for STMicroelectronics or a software update for such device, must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. +3. Neither the name of STMicroelectronics nor the names of other contributors to this software package may be used to endorse or promote products derived from this software package or part thereof without specific written permission. +4. This software package or any part thereof, including modifications and/or derivative works of this software package, must be used and execute solely and exclusively on or in combination with a microcontroller or a microprocessor devices manufactured by or for STMicroelectronics. +5. No use, reproduction or redistribution of this software package partially or totally may be done in any manner that would subject this software package to any Open Source Terms (as defined below). +6. Some portion of the software package may contain software subject to Open Source Terms (as defined below) applicable for each such portion (“Open Source Software”), as further specified in the software package. Such Open Source Software is supplied under the applicable Open Source Terms and is not subject to the terms and conditions of license hereunder. “Open Source Terms” shall mean any open source license which requires as part of distribution of software that the source code of such software is distributed therewith or otherwise made available, or open source license that substantially complies with the Open Source definition specified at www.opensource.org and any other comparable open source license such as for example GNU General Public License (GPL), Eclipse Public License (EPL), Apache Software License, BSD license and MIT license. +7. This software package may also include third party software as expressly specified in the software package subject to specific license terms from such third parties. Such third party software is supplied under such specific license terms and is not subject to the terms and conditions of license hereunder. By installing copying, downloading, accessing or otherwise using this software package, the recipient agrees to be bound by such license terms with regard to such third party software. +8. STMicroelectronics has no obligation to provide any maintenance, support or updates for the software package. +9. The software package is and will remain the exclusive property of STMicroelectronics and its licensors. The recipient will not take any action that jeopardizes STMicroelectronics and its licensors' proprietary rights or acquire any rights in the software package, except the limited rights specified hereunder. +10. The recipient shall comply with all applicable laws and regulations affecting the use of the software package or any part thereof including any applicable export control law or regulation. +11. Redistribution and use of this software package partially or any part thereof other than as permitted under this license is void and will automatically terminate your rights under this license. + +THIS SOFTWARE PACKAGE IS PROVIDED BY STMICROELECTRONICS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS, IMPLIED OR STATUTORY WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS ARE DISCLAIMED TO THE FULLEST EXTENT PERMITTED BY LAW. IN NO EVENT SHALL STMICROELECTRONICS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE PACKAGE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +EXCEPT AS EXPRESSLY PERMITTED HEREUNDER AND SUBJECT TO THE APPLICABLE LICENSING TERMS FOR ANY THIRD-PARTY SOFTWARE INCORPORATED IN THE SOFTWARE PACKAGE AND OPEN SOURCE TERMS AS APPLICABLE, NO LICENSE OR OTHER RIGHTS, WHETHER EXPRESS OR IMPLIED, ARE GRANTED UNDER ANY PATENT OR OTHER INTELLECTUAL PROPERTY RIGHTS OF STMICROELECTRONICS OR ANY THIRD PARTY. diff --git a/meta-st/meta-st-stm32mpu-hce/conf/eula/stm32mp1-hce b/meta-st/meta-st-stm32mpu-hce/conf/eula/stm32mp1-hce new file mode 100644 index 0000000..5fbc604 --- /dev/null +++ b/meta-st/meta-st-stm32mpu-hce/conf/eula/stm32mp1-hce @@ -0,0 +1,97 @@ +SLA0048 Rev4/March 2018 + +BY INSTALLING COPYING, DOWNLOADING, ACCESSING OR OTHERWISE USING THIS SOFTWARE PACKAGE OR ANY PART THEREOF (AND THE RELATED DOCUMENTATION) FROM STMICROELECTRONICS INTERNATIONAL N.V, SWISS BRANCH AND/OR ITS AFFILIATED COMPANIES (STMICROELECTRONICS), THE RECIPIENT, ON BEHALF OF HIMSELF OR HERSELF, OR ON BEHALF OF ANY ENTITY BY WHICH SUCH RECIPIENT IS EMPLOYED AND/OR ENGAGED AGREES TO BE BOUND BY THIS SOFTWARE PACKAGE LICENSE AGREEMENT. + +Under STMicroelectronics’ intellectual property rights and subject to applicable licensing terms for any third-party software incorporated in this software package and applicable Open Source Terms (as defined here below), the redistribution, reproduction and use in source and binary forms of the software package or any part thereof, with or without modification, are permitted provided that the following conditions are met: +1. Redistribution of source code (modified or not) must retain any copyright notice, this list of conditions and the following disclaimer. +2. Redistributions in binary form, except as embedded into microcontroller or microprocessor device manufactured by or for STMicroelectronics or a software update for such device, must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. +3. Neither the name of STMicroelectronics nor the names of other contributors to this software package may be used to endorse or promote products derived from this software package or part thereof without specific written permission. +4. This software package or any part thereof, including modifications and/or derivative works of this software package, must be used and execute solely and exclusively on or in combination with a microcontroller or a microprocessor devices manufactured by or for STMicroelectronics. +5. No use, reproduction or redistribution of this software package partially or totally may be done in any manner that would subject this software package to any Open Source Terms (as defined below). +6. Some portion of the software package may contain software subject to Open Source Terms (as defined below) applicable for each such portion (“Open Source Software”), as further specified in the software package. Such Open Source Software is supplied under the applicable Open Source Terms and is not subject to the terms and conditions of license hereunder. “Open Source Terms” shall mean any open source license which requires as part of distribution of software that the source code of such software is distributed therewith or otherwise made available, or open source license that substantially complies with the Open Source definition specified at www.opensource.org and any other comparable open source license such as for example GNU General Public License (GPL), Eclipse Public License (EPL), Apache Software License, BSD license and MIT license. +7. This software package may also include third party software as expressly specified in the software package subject to specific license terms from such third parties. Such third party software is supplied under such specific license terms and is not subject to the terms and conditions of license hereunder. By installing copying, downloading, accessing or otherwise using this software package, the recipient agrees to be bound by such license terms with regard to such third party software. +8. STMicroelectronics has no obligation to provide any maintenance, support or updates for the software package. +9. The software package is and will remain the exclusive property of STMicroelectronics and its licensors. The recipient will not take any action that jeopardizes STMicroelectronics and its licensors' proprietary rights or acquire any rights in the software package, except the limited rights specified hereunder. +10. The recipient shall comply with all applicable laws and regulations affecting the use of the software package or any part thereof including any applicable export control law or regulation. +11. Redistribution and use of this software package partially or any part thereof other than as permitted under this license is void and will automatically terminate your rights under this license. + +THIS SOFTWARE PACKAGE IS PROVIDED BY STMICROELECTRONICS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS, IMPLIED OR STATUTORY WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS ARE DISCLAIMED TO THE FULLEST EXTENT PERMITTED BY LAW. IN NO EVENT SHALL STMICROELECTRONICS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE PACKAGE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +EXCEPT AS EXPRESSLY PERMITTED HEREUNDER AND SUBJECT TO THE APPLICABLE LICENSING TERMS FOR ANY THIRD-PARTY SOFTWARE INCORPORATED IN THE SOFTWARE PACKAGE AND OPEN SOURCE TERMS AS APPLICABLE, NO LICENSE OR OTHER RIGHTS, WHETHER EXPRESS OR IMPLIED, ARE GRANTED UNDER ANY PATENT OR OTHER INTELLECTUAL PROPERTY RIGHTS OF STMICROELECTRONICS OR ANY THIRD PARTY. + +############################################################################### + +Vivante End User Software License Terms + +The following are the terms to be agreed to by end users of Vivante Software licensed herein: + +Copyright 2003-2017 Vivante Corporation, all rights reserved. + +Use, reproduction and redistribution of this software in binary form, without modification and solely for use in conjunction with STMicroelectronics semiconductor chips with the Linux operating system environment that contain Vivante Corporation’s technology, are permitted provided that the following conditions are met: + +* Redistributions must reproduce the above copyright notice, this list of conditions and the following disclaimers in the documentation and/or other materials provided with the distribution. + +* Neither the name nor trademarks of STMicroelectronics International N.V. nor any other STMicroelectronics company (nor Vivante Corporation unless permission is granted separately by Vivante Corporation) may be used to endorse or promote products derived from this software without specific prior written permission. + +* No reverse engineering, decompilation or disassembly of this software is permitted. + +* No use, reproduction or redistribution of this software may be done in any manner that may cause this software to be redistributed as part of the Linux kernel or in any other manner that would subject this software to the terms of the GNU General Public License, the GNU Lesser General Public License, or any other copyleft license. + +DISCLAIMERS: + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER(S) "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT, ARE DISCLAIMED. IN NO EVENT SHALL STMICROELECTRONICS INTERNATIONAL N.V. NOR ANY OTHER STMICROELECTRONICS COMPANY (NOR VIVANTE CORPORATION) BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +THE DELIVERY OF THIS SOFTWARE DOES NOT CONVEY ANY LICENSE, WHETHER EXPRESS OR IMPLIED, TO ANY THIRD-PARTY INTELLECTUAL PROPERTY RIGHTS. + +EXCEPT THE LIMITED RIGHT TO USE, REPRODUCE AND REDISTRIBUTE THIS SOFTWARE IN BINARY FORM, NO LICENSE OR OTHER RIGHTS, WHETHER EXPRESS OR IMPLIED, ARE GRANTED UNDER ANY PATENT OR OTHER INTELLECTUAL PROPERTY RIGHTS OF STMICROELECTRONICS INTERNATIONAL N.V. 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WITHOUT LIMITING THE FOREGOING, EXPORT, RE-EXPORT, OR TRANSFER OF THE SOFTWARE TO CUBA, IRAN, NORTH KOREA, SUDAN, AND SYRIA IS PROHIBITED. diff --git a/meta-st/meta-st-stm32mpu-hce/conf/layer.conf b/meta-st/meta-st-stm32mpu-hce/conf/layer.conf new file mode 100644 index 0000000..b3d85fc --- /dev/null +++ b/meta-st/meta-st-stm32mpu-hce/conf/layer.conf @@ -0,0 +1,23 @@ +# We have a conf and classes directory, add to BBPATH +BBPATH .= ":${LAYERDIR}" + +# We have a recipes-* directories, add to BBFILES +BBFILES += "${LAYERDIR}/recipes-*/*/*.bb \ + ${LAYERDIR}/recipes-*/*/*.bbappend" + +BBFILE_COLLECTIONS += "stm-st-stm32mp-hce" +BBFILE_PATTERN_stm-st-stm32mp-hce := "^${LAYERDIR}/" +BBFILE_PRIORITY_stm-st-stm32mp-hce = "12" + +EULA_FILE_ST_stm32mpcommonmx = "${LAYERDIR}/conf/eula/${MACHINE}" +EULA_FILE_ST_MD5SUM_stm32mpcommonmx = "8b505090fb679839cefbcc784afe8ce9" + +# Set a variable to get the STM32MP MX BSP location +STM32MP_BASE = "${LAYERDIR}" + +# This should only be incremented on significant changes that will +# cause compatibility issues with other layers +LAYERVERSION_stm-st-stm32mp-hce = "1" +LAYERSERIES_COMPAT_stm-st-stm32mp-hce = "zeus dunfell" + +LAYERDEPENDS_stm-st-stm32mp-hce = "stm-st-stm32mp-mx core openembedded-layer" diff --git a/meta-st/meta-st-stm32mpu-hce/conf/machine/stm32mp1-hce.conf b/meta-st/meta-st-stm32mpu-hce/conf/machine/stm32mp1-hce.conf new file mode 100644 index 0000000..abbd949 --- /dev/null +++ b/meta-st/meta-st-stm32mpu-hce/conf/machine/stm32mp1-hce.conf @@ -0,0 +1,111 @@ +#@TYPE: Machine +#@NAME: stm32mp1-hce +#@DESCRIPTION: Configuration for HCE(Hyundai Construction Equipment ) +#@NEEDED_BSPLAYERS: layers/meta-openembedded/meta-oe layers/meta-openembedded/meta-python layers/meta-st/meta-st-stm32mp-addons + +include conf/machine/include/st-machine-common-stm32mp.inc +include conf/machine/include/st-machine-providers-stm32mp.inc + + +# Define specific common machine name +MACHINEOVERRIDES .= ":stm32mpcommonmx" + +# ========================================================================= +# Chip architecture +# ========================================================================= +DEFAULTTUNE = "cortexa7thf-neon-vfpv4" +include conf/machine/include/tune-cortexa7.inc + +# ========================================================================= +# Machine settings +# ========================================================================= +STM32MP_DEVICETREE = "${CUBEMX_DTB}" + +# ========================================================================= +# Machine features (default for stm32mp1 like) +# ========================================================================= +MACHINE_FEATURES += "splashscreen" +MACHINE_FEATURES += "watchdog" +MACHINE_FEATURES += "${@'gpu' if d.getVar('ACCEPT_EULA_'+d.getVar('MACHINE')) == '1' else ''}" +MACHINE_FEATURES += "m4copro" + +# ========================================================================= +# Device Storage +# ========================================================================= +# Enable the board device storage support with CUBEMX_DTB according to BOOTDEVICE_LABELS +#DEVICE_BOARD_ENABLE_NAND += "${@bb.utils.contains('BOOTDEVICE_LABELS', 'nand-4-256', '${CUBEMX_DTB}', '', d)}" +#DEVICE_BOARD_ENABLE_NOR += "${@bb.utils.contains('BOOTDEVICE_LABELS', 'nor-sdcard' , '${CUBEMX_DTB}', '', d)}" +DEVICE_BOARD_ENABLE_EMMC += "${@bb.utils.contains('BOOTDEVICE_LABELS', 'emmc', '${CUBEMX_DTB}', '', d)}" +DEVICE_BOARD_ENABLE_SDCARD += "${@bb.utils.contains('BOOTDEVICE_LABELS', 'sdcard', '${CUBEMX_DTB}', '', d)}" + +# ========================================================================= +# Flashlayout +# ========================================================================= +# Set the FLASHLAYOUT_TYPE_LABELS to CUBEMX_DTB according to BOOTDEVICE_LABELS +FLASHLAYOUT_TYPE_LABELS_emmc = "${@bb.utils.contains('BOOTDEVICE_LABELS', 'emmc', '${CUBEMX_DTB}', '', d)}" +#FLASHLAYOUT_TYPE_LABELS_nand-4-256 = "${@bb.utils.contains('BOOTDEVICE_LABELS', 'nand-4-256', '${CUBEMX_DTB}', '', d)}" +#FLASHLAYOUT_TYPE_LABELS_nor-sdcard = "${@bb.utils.contains('BOOTDEVICE_LABELS', 'nor-sdcard' , '${CUBEMX_DTB}', '', d)}" +FLASHLAYOUT_TYPE_LABELS_sdcard = "${@bb.utils.contains('BOOTDEVICE_LABELS', 'sdcard', '${CUBEMX_DTB}', '', d)}" + +# Specific settings for 'extensible' and 'deleteall' configurations +FLASHLAYOUT_CONFIG_LABELS_deleteall = "cubemx" +FLASHLAYOUT_TYPE_LABELS_deleteall_cubemx = "${CUBEMX_DTB}" +FLASHLAYOUT_TYPE_LABELS_extensible = "${CUBEMX_DTB}" + +# ========================================================================= +# CubeMX extra config +# ========================================================================= +# Set specific subdir path by components for each device tree file location +# within CUBEMX_PROJECT project folder +CUBEMX_DTB_PATH_TFA = "tf-a" +CUBEMX_DTB_PATH_TFA_SB = "tf-a" +CUBEMX_DTB_PATH_UBOOT = "u-boot" +CUBEMX_DTB_PATH_LINUX = "kernel" +CUBEMX_DTB_PATH_OPTEEOS = "optee-os" + + +# ========================================================================= +# Set preferred version +PREFERRED_VERSION_greengrass = "1.11.0" + +########################################################################### +# +# User machine customization sections +# +########################################################################### + +# Boot Scheme +# ========================================================================= +BOOTSCHEME_LABELS += "trusted" +#BOOTSCHEME_LABELS += "optee" + +# Boot Device Choice +# ========================================================================= +# Define the boot device supported +BOOTDEVICE_LABELS += "sdcard" +BOOTDEVICE_LABELS += "emmc" +#BOOTDEVICE_LABELS += "nand-4-256" +#BOOTDEVICE_LABELS += "nor-sdcard" + +# Support Feature Choice +# ========================================================================= +# Define the features to enable on board +# MACHINE_FEATURES += "bluetooth" +# MACHINE_FEATURES += "wifi" + +# Specific firmwares and kernel modules configuration +# ========================================================================= +# Set the list of kernel module to be auto-loaded during boot +#KERNEL_MODULE_AUTOLOAD += "" + +# Set Bluetooth related package list needed when 'bluetooth' feature is enabled +# BLUETOOTH_LIST += "linux-firmware-bluetooth-bcm4343" + +# Set Wifi related package list needed when 'wifi' feature is enabled +# WIFI_LIST += "linux-firmware-bcm43430" + +# CubeMX Project Config +# ========================================================================= +# Assign CubeMX Board devicetree and project path name +CUBEMX_DTB = "stm32mp157c-hce-mx" +CUBEMX_PROJECT = "mx/STM32MP157C-DK2/DeviceTree/hce" diff --git a/meta-st/meta-st-stm32mpu-hce/hello_world_example/hello_word_example b/meta-st/meta-st-stm32mpu-hce/hello_world_example/hello_word_example new file mode 100755 index 0000000..644d011 Binary files /dev/null and b/meta-st/meta-st-stm32mpu-hce/hello_world_example/hello_word_example differ diff --git a/meta-st/meta-st-stm32mpu-hce/hello_world_example/hello_world_example b/meta-st/meta-st-stm32mpu-hce/hello_world_example/hello_world_example new file mode 100755 index 0000000..644d011 Binary files /dev/null and b/meta-st/meta-st-stm32mpu-hce/hello_world_example/hello_world_example differ diff --git a/meta-st/meta-st-stm32mpu-hce/hello_world_example/hello_world_example.c b/meta-st/meta-st-stm32mpu-hce/hello_world_example/hello_world_example.c new file mode 100644 index 0000000..29c80ce --- /dev/null +++ b/meta-st/meta-st-stm32mpu-hce/hello_world_example/hello_world_example.c @@ -0,0 +1,25 @@ +// SPDX-identifier: GPL-2.0 +/* + * Copyright (C) STMicroelectronics SA 2018 + * + * Authors: Jean-Christophe Trotin + * + */ + +#include +#include + +int main(int argc, char **argv) +{ + int i =11; + + printf("\nUser space example: hello world from STMicroelectronics\n"); + setbuf(stdout,NULL); + while (i--) { + printf("%i ", i); + sleep(1); + } + printf("\nUser space example: goodbye from STMicroelectronics\n"); + + return(0); +} diff --git a/meta-st/meta-st-stm32mpu-hce/hello_world_example/oe-logs b/meta-st/meta-st-stm32mpu-hce/hello_world_example/oe-logs new file mode 120000 index 0000000..6c8b789 --- /dev/null +++ b/meta-st/meta-st-stm32mpu-hce/hello_world_example/oe-logs @@ -0,0 +1 @@ +/home/builder/Workspace/Distribution-Package/openstlinux-5.4-dunfell-mp1-20-06-24/build-openstlinuxweston-stm32mp1-hce/tmp-glibc/work/cortexa7t2hf-neon-vfpv4-ostl-linux-gnueabi/helloworld/1.0-r0/temp \ No newline at end of file diff --git a/meta-st/meta-st-stm32mpu-hce/hello_world_example/oe-workdir b/meta-st/meta-st-stm32mpu-hce/hello_world_example/oe-workdir new file mode 120000 index 0000000..355a240 --- /dev/null +++ b/meta-st/meta-st-stm32mpu-hce/hello_world_example/oe-workdir @@ -0,0 +1 @@ +/home/builder/Workspace/Distribution-Package/openstlinux-5.4-dunfell-mp1-20-06-24/build-openstlinuxweston-stm32mp1-hce/tmp-glibc/work/cortexa7t2hf-neon-vfpv4-ostl-linux-gnueabi/helloworld/1.0-r0 \ No newline at end of file diff --git a/meta-st/meta-st-stm32mpu-hce/mx/STM32MP157C-DK2/DeviceTree/hce/kernel/stm32mp157c-hce-mx.dts b/meta-st/meta-st-stm32mpu-hce/mx/STM32MP157C-DK2/DeviceTree/hce/kernel/stm32mp157c-hce-mx.dts new file mode 100755 index 0000000..223d9d0 --- /dev/null +++ b/meta-st/meta-st-stm32mpu-hce/mx/STM32MP157C-DK2/DeviceTree/hce/kernel/stm32mp157c-hce-mx.dts @@ -0,0 +1,1524 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */ +/* + * Copyright (C) STMicroelectronics 2020 - All Rights Reserved + * Author: STM32CubeMX code generation for STMicroelectronics. + */ + +/* For more information on Device Tree configuration, please refer to + * https://wiki.st.com/stm32mpu/wiki/Category:Device_tree_configuration + */ + +/dts-v1/; +#include + +#include "stm32mp157.dtsi" +#include "stm32mp15xc.dtsi" +#include "stm32mp15xxac-pinctrl.dtsi" +#include "stm32mp157-m4-srm.dtsi" + +/* USER CODE BEGIN includes */ +#include +#include +/* USER CODE END includes */ + +#define MBED_OS_DEBUG_UASRT3 0 +#define IECN_MAX_3109 1 + +#define IECN_SPI5_MAX3109_A7_LINUX 1 +#define IECN_SPI1_MAX3109_A7_LINUX 1 + + +/ { + model = "STMicroelectronics STM32MP157C-DK2 STM32CubeMX board"; + compatible = "st,stm32mp157c-hce-mx", "st,stm32mp157"; + + memory@c0000000 { + device_type = "memory"; + reg = <0xc0000000 0x20000000>; + + /* USER CODE BEGIN memory */ + /* USER CODE END memory */ + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + /* USER CODE BEGIN reserved-memory */ + + mcuram2:mcuram2@10000000{ + compatible = "shared-dma-pool"; + reg = <0x10000000 0x40000>; + no-map; + }; + + vdev0vring0:vdev0vring0@10040000{ + compatible = "shared-dma-pool"; + reg = <0x10040000 0x1000>; + no-map; + }; + + vdev0vring1:vdev0vring1@10041000{ + compatible = "shared-dma-pool"; + reg = <0x10041000 0x1000>; + no-map; + }; + + vdev0buffer:vdev0buffer@10042000{ + compatible = "shared-dma-pool"; + reg = <0x10042000 0x4000>; + no-map; + }; + + mcuram:mcuram@30000000{ + compatible = "shared-dma-pool"; + reg = <0x30000000 0x40000>; + no-map; + }; + + retram:retram@38000000{ + compatible = "shared-dma-pool"; + reg = <0x38000000 0x10000>; + no-map; + }; + + gpu_reserved:gpu@da000000{ + reg = <0xda000000 0x4000000>; + no-map; + }; + + optee_memory:optee@0xde000000{ + reg = <0xde000000 0x02000000>; + no-map; + status = "okay"; + }; + /* USER CODE END reserved-memory */ + }; + + /* USER CODE BEGIN root */ + + led{ + compatible = "gpio-leds"; + + blue{ + label = "heartbeat"; + gpios = <&gpiod 11 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + default-state = "off"; + }; + }; + + + +#if 0 + sound{ + compatible = "audio-graph-card"; + label = "STM32MP1-DK"; + routing = "Playback", "MCLK", + "Capture", "MCLK", + "MICL", "Mic Bias"; + dais = <&sai2a_port &sai2b_port &i2s2_port>; + status = "okay"; + }; +#endif + + usb_phy_tuning:usb-phy-tuning{ + st,hs-dc-level = <2>; + st,fs-rftime-tuning; + st,hs-rftime-reduction; + st,hs-current-trim = <15>; + st,hs-impedance-trim = <1>; + st,squelch-level = <3>; + st,hs-rx-offset = <2>; + st,no-lsfs-sc; + }; + + vin:vin{ + compatible = "regulator-fixed"; + regulator-name = "vin"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + }; + + aliases{ + ethernet0 = ðernet0; + serial0 = &uart4; + serial1 = &usart3; + serial2 = &uart7; + serial3 = &usart2; + /* Added by mirika@SDT */ + mmc0 = &sdmmc1; + mmc1 = &sdmmc2; + mmc2 = &sdmmc3; + + }; + + chosen{ + stdout-path = "serial0:115200n8"; + }; + + wifi_pwrseq:wifi-pwrseq{ + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&gpioh 4 GPIO_ACTIVE_LOW>; + }; + /* USER CODE END root */ + + clocks { + + /* USER CODE BEGIN clocks */ + /* USER CODE END clocks */ + +#ifndef CONFIG_STM32MP1_TRUSTED + clk_lsi: clk-lsi { + clock-frequency = <32000>; + }; + clk_hsi: clk-hsi { + clock-frequency = <64000000>; + }; + clk_csi: clk-csi { + clock-frequency = <4000000>; + }; + clk_lse: clk-lse { + clock-frequency = <32768>; + }; + clk_hse: clk-hse { + clock-frequency = <24000000>; + }; +#endif /*CONFIG_STM32MP1_TRUSTED*/ +#if 1 + spi_uart_clk: osc_max3109 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <3686400>; + //clock-output-names = "osc" + }; +#endif + + }; +}; /*root*/ + +/* modified by SDT */ +&cpu0_opp_table { + opp-650000000 { + opp-hz = /bits/ 64 <650000000>; + opp-microvolt = <1200000>; + opp-supported-hw = <0x1>; + }; +}; + + +&pinctrl { + u-boot,dm-pre-reloc; + + adc_pins_mx: adc_mx-0 { + pins { + pinmux = , /* ADC1_INP18 */ + ; /* ADC1_INP19 */ + }; + }; + + adc_sleep_pins_mx: adc_sleep_mx-0 { + pins { + pinmux = , /* ADC1_INP18 */ + ; /* ADC1_INP19 */ + }; + }; + + eth1_pins_mx: eth1_mx-0 { + pins1 { + pinmux = , /* ETH1_RX_CLK */ + , /* ETH1_RX_CTL */ + , /* ETH1_RXD2 */ + , /* ETH1_RXD3 */ + , /* ETH1_RXD0 */ + ; /* ETH1_RXD1 */ + bias-disable; + }; + pins2 { + pinmux = ; /* ETH1_MDIO */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins3 { + pinmux = , /* ETH1_TX_CTL */ + , /* ETH1_MDC */ + , /* ETH1_TXD2 */ + , /* ETH1_TXD3 */ + , /* ETH1_GTX_CLK */ + , /* ETH1_CLK125 */ + , /* ETH1_TXD0 */ + ; /* ETH1_TXD1 */ + bias-disable; + drive-push-pull; + slew-rate = <2>; + }; + }; + + eth1_sleep_pins_mx: eth1_sleep_mx-0 { + pins { + pinmux = , /* ETH1_RX_CLK */ + , /* ETH1_MDIO */ + , /* ETH1_RX_CTL */ + , /* ETH1_RXD2 */ + , /* ETH1_RXD3 */ + , /* ETH1_TX_CTL */ + , /* ETH1_MDC */ + , /* ETH1_TXD2 */ + , /* ETH1_RXD0 */ + , /* ETH1_RXD1 */ + , /* ETH1_TXD3 */ + , /* ETH1_GTX_CLK */ + , /* ETH1_CLK125 */ + , /* ETH1_TXD0 */ + ; /* ETH1_TXD1 */ + }; + }; + + // Added by SDT + fdcan1_pins_mx: fdcan1_mx-0 { + pins1 { + pinmux = ; /* FDCAN1_RX */ + bias-disable; + }; + pins2 { + pinmux = ; /* FDCAN1_TX */ + bias-disable; + drive-push-pull; + slew-rate = <1>; + }; + }; + + fdcan1_sleep_pins_mx: fdcan1_sleep_mx-0 { + pins { + pinmux = , /* FDCAN1_RX */ + ; /* FDCAN1_TX */ + }; + }; + + // addrd by mirika@SDT + fdcan2_pins_mx: fdcan2_mx-0 { + pins1 { + pinmux = ; /* FDCAN2_RX */ + bias-disable; + }; + pins2 { + pinmux = ; /* FDCAN2_TX */ + bias-disable; + drive-push-pull; + slew-rate = <1>; + }; + }; + + fdcan2_sleep_pins_mx: fdcan2_sleep_mx-0 { + pins { + pinmux = , /* FDCAN2_RX */ + ; /* FDCAN2_TX */ + }; + }; + // END + + hdmi_cec_pins_mx: hdmi_cec_mx-0 { + pins { + pinmux = ; /* CEC */ + bias-disable; + drive-open-drain; + slew-rate = <0>; + }; + }; + + hdmi_cec_sleep_pins_mx: hdmi_cec_sleep_mx-0 { + pins { + pinmux = ; /* CEC */ + }; + }; + + i2c1_pins_mx: i2c1_mx-0 { + pins { + pinmux = , /* I2C1_SCL */ + ; /* I2C1_SDA */ + bias-disable; + drive-open-drain; + slew-rate = <0>; + }; + }; + + i2c1_sleep_pins_mx: i2c1_sleep_mx-0 { + pins { + pinmux = , /* I2C1_SCL */ + ; /* I2C1_SDA */ + }; + }; + + i2s2_pins_mx: i2s2_mx-0 { + pins { + pinmux = , /* I2S2_CK */ + , /* I2S2_WS */ + ; /* I2S2_SDO */ + bias-disable; + drive-push-pull; + slew-rate = <1>; + }; + }; + + i2s2_sleep_pins_mx: i2s2_sleep_mx-0 { + pins { + pinmux = , /* I2S2_CK */ + , /* I2S2_WS */ + ; /* I2S2_SDO */ + }; + }; + + rtc_pins_mx: rtc_mx-0 { + pins { + pinmux = ; /* RTC_LSCO */ + }; + }; + + rtc_sleep_pins_mx: rtc_sleep_mx-0 { + pins { + pinmux = ; /* RTC_LSCO */ + }; + }; + + sai2a_pins_mx: sai2a_mx-0 { + pins { + pinmux = , /* SAI2_MCLK_A */ + , /* SAI2_SCK_A */ + , /* SAI2_SD_A */ + ; /* SAI2_FS_A */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + }; + + sai2a_sleep_pins_mx: sai2a_sleep_mx-0 { + pins { + pinmux = , /* SAI2_MCLK_A */ + , /* SAI2_SCK_A */ + , /* SAI2_SD_A */ + ; /* SAI2_FS_A */ + }; + }; + + sai2b_pins_mx: sai2b_mx-0 { + pins { + pinmux = ; /* SAI2_SD_B */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + }; + + sai2b_sleep_pins_mx: sai2b_sleep_mx-0 { + pins { + pinmux = ; /* SAI2_SD_B */ + }; + }; + + sdmmc1_pins_mx: sdmmc1_mx-0 { + u-boot,dm-pre-reloc; + pins1 { + u-boot,dm-pre-reloc; + pinmux = , /* SDMMC1_D0 */ + , /* SDMMC1_D1 */ + , /* SDMMC1_D2 */ + , /* SDMMC1_D3 */ + ; /* SDMMC1_CMD */ + bias-disable; + drive-push-pull; + slew-rate = <1>; + }; + pins2 { + u-boot,dm-pre-reloc; + pinmux = ; /* SDMMC1_CK */ + bias-disable; + drive-push-pull; + slew-rate = <2>; + }; + }; + + sdmmc1_opendrain_pins_mx: sdmmc1_opendrain_mx-0 { + u-boot,dm-pre-reloc; + pins1 { + u-boot,dm-pre-reloc; + pinmux = , /* SDMMC1_D0 */ + , /* SDMMC1_D1 */ + , /* SDMMC1_D2 */ + ; /* SDMMC1_D3 */ + bias-disable; + drive-push-pull; + slew-rate = <1>; + }; + pins2 { + u-boot,dm-pre-reloc; + pinmux = ; /* SDMMC1_CK */ + bias-disable; + drive-push-pull; + slew-rate = <2>; + }; + pins3 { + u-boot,dm-pre-reloc; + pinmux = ; /* SDMMC1_CMD */ + bias-disable; + drive-open-drain; + slew-rate = <1>; + }; + }; + + sdmmc1_sleep_pins_mx: sdmmc1_sleep_mx-0 { + u-boot,dm-pre-reloc; + pins { + u-boot,dm-pre-reloc; + pinmux = , /* SDMMC1_D0 */ + , /* SDMMC1_D1 */ + , /* SDMMC1_D2 */ + , /* SDMMC1_D3 */ + , /* SDMMC1_CK */ + ; /* SDMMC1_CMD */ + }; + }; + + sdmmc2_pins_mx: sdmmc2_mx-0 { + pins1 { + pinmux = , /* SDMMC2_D0 */ + , /* SDMMC2_D1 */ + , /* SDMMC2_D2 */ + , /* SDMMC2_D3 */ + ; /* SDMMC2_CMD */ + slew-rate = <1>; + drive-push-pull; + bias-pull-up; + }; + pins2 { + pinmux = ; /* SDMMC2_CK */ + slew-rate = <2>; + drive-push-pull; + bias-pull-up; + }; + }; + + sdmmc2_opendrain_pins_mx: sdmmc2_opendrain_mx-0 { + pins1 { + pinmux = , /* SDMMC2_D2 */ + , /* SDMMC2_D3 */ + , /* SDMMC2_D0 */ + ; /* SDMMC2_D1 */ + bias-disable; + drive-push-pull; + slew-rate = <1>; + }; + pins2 { + pinmux = ; /* SDMMC2_CK */ + bias-disable; + drive-push-pull; + slew-rate = <2>; + }; + pins3 { + pinmux = ; /* SDMMC2_CMD */ + bias-disable; + drive-open-drain; + slew-rate = <1>; + }; + }; + + sdmmc2_sleep_pins_mx: sdmmc2_sleep_mx-0 { + pins { + pinmux = , /* SDMMC2_D2 */ + , /* SDMMC2_D3 */ + , /* SDMMC2_D0 */ + , /* SDMMC2_D1 */ + , /* SDMMC2_CK */ + ; /* SDMMC2_CMD */ + }; + }; + +#if IECN_SPI5_MAX3109_A7_LINUX + spi5_pins_mx: spi5_mx-0 { + pins { + pinmux = , /* SPI5_MISO */ + , /* SPI5_MOSI */ + ; /* SPI5_SCK */ + bias-disable; + drive-push-pull; + slew-rate = <1>; + }; + + }; + + spi5_sleep_pins_mx: spi5_sleep_mx-0 { + pins { + pinmux = , /* SPI5_MISO */ + , /* SPI5_MOSI */ + ; /* SPI5_SCK */ + }; + }; +#else + +#endif + + uart4_pins_mx: uart4_mx-0 { + u-boot,dm-pre-reloc; + pins1 { + u-boot,dm-pre-reloc; + pinmux = ; /* UART4_RX */ + bias-disable; + }; + pins2 { + u-boot,dm-pre-reloc; + pinmux = ; /* UART4_TX */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + }; + + uart4_sleep_pins_mx: uart4_sleep_mx-0 { + u-boot,dm-pre-reloc; + pins { + u-boot,dm-pre-reloc; + pinmux = , /* UART4_RX */ + ; /* UART4_TX */ + }; + }; + + usart2_pins_mx: usart2_mx-0 { + pins1 { + pinmux = , /* USART2_CTS */ + ; /* USART2_RX */ + bias-disable; + }; + pins2 { + pinmux = , /* USART2_RTS */ + ; /* USART2_TX */ + bias-disable; + drive-push-pull; + slew-rate = <3>; + }; + }; + + usart2_sleep_pins_mx: usart2_sleep_mx-0 { + pins { + pinmux = , /* USART2_CTS */ + , /* USART2_RTS */ + , /* USART2_TX */ + ; /* USART2_RX */ + }; + }; + + /* USER CODE BEGIN pinctrl */ + stusb1600_pins_a: stusb1600-0 { + pins { + pinmux = ; + bias-pull-up; + }; + }; + + // Added by SDT + sdmmc3_mx_pins_a: sdmmc3_mx-0 { + pins1 { + pinmux = , /* SDMMC3_D0 */ + , /* SDMMC3_D1 */ + , /* SDMMC3_D2 */ + , /* SDMMC3_D3 */ + ; /* SDMMC3_CMD */ + slew-rate = <1>; + drive-push-pull; + bias-pull-up; + }; + pins2 { + pinmux = ; /* SDMMC3_CK */ + slew-rate = <2>; + drive-push-pull; + bias-pull-up; + }; + }; + + sdmmc3_mx_od_pins_a: sdmmc3_mx-od-0 { + pins1 { + pinmux = , /* SDMMC3_D0 */ + , /* SDMMC3_D1 */ + , /* SDMMC3_D2 */ + ; /* SDMMC3_D3 */ + slew-rate = <1>; + drive-push-pull; + bias-pull-up; + }; + pins2 { + pinmux = ; /* SDMMC3_CK */ + slew-rate = <2>; + drive-push-pull; + bias-pull-up; + }; + pins3 { + pinmux = ; /* SDMMC2_CMD */ + slew-rate = <1>; + drive-open-drain; + bias-pull-up; + }; + }; + + sdmmc3_mx_sleep_pins_a: sdmmc3_mx-sleep-0 { + pins { + pinmux = , /* SDMMC3_D0 */ + , /* SDMMC3_D1 */ + , /* SDMMC3_D2 */ + , /* SDMMC3_D3 */ + , /* SDMMC3_CK */ + ; /* SDMMC3_CMD */ + }; + }; + /* USER CODE END pinctrl */ +}; + +&pinctrl_z { + u-boot,dm-pre-reloc; + + i2c4_pins_z_mx: i2c4_mx-0 { + u-boot,dm-pre-reloc; + pins { + u-boot,dm-pre-reloc; + pinmux = , /* I2C4_SCL */ + ; /* I2C4_SDA */ + bias-disable; + drive-open-drain; + slew-rate = <0>; + }; + }; + + i2c4_sleep_pins_z_mx: i2c4_sleep_mx-0 { + u-boot,dm-pre-reloc; + pins { + u-boot,dm-pre-reloc; + pinmux = , /* I2C4_SCL */ + ; /* I2C4_SDA */ + }; + }; + + /* USER CODE BEGIN pinctrl_z */ +#if IECN_SPI1_MAX3109_A7_LINUX + spi1_pins_z_mx: spi1_pins_z_mx-0 { + pins { + pinmux = , /* SPI1_MISO */ + , /* SPI1_MOSI */ + ; /* SPI1_SCK */ + // ; /* SPI1_NSS */ + bias-disable; + drive-push-pull; + slew-rate = <1>; + }; + }; + + spi1_sleep_pins_z_mx:spi1_sleep_pins_z_mx-0 { + pins { + pinmux = , /* SPI1_SCK */ + , /* SPI1_MISO */ + ; /* SPI1_MOSI */ + // ; /* SPI1_NSS */ + }; + }; +#else + /* SPI1 IOLINK M4 Interface */ + +#endif + /* USER CODE END pinctrl_z */ +}; +&m4_rproc{ + /*Restriction: "memory-region" property is not managed - please to use User-Section if needed*/ + mboxes = <&ipcc 0>, <&ipcc 1>, <&ipcc 2>; + mbox-names = "vq0", "vq1", "shutdown"; + status = "okay"; + + /* USER CODE BEGIN m4_rproc */ + memory-region = <&retram>, <&mcuram>, <&mcuram2>, <&vdev0vring0>, + <&vdev0vring1>, <&vdev0buffer>; + interrupt-parent = <&exti>; + interrupts = <68 1>; + wakeup-source; + /* USER CODE END m4_rproc */ +}; +&adc{ + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&adc_pins_mx>; + pinctrl-1 = <&adc_sleep_pins_mx>; + status = "okay"; + + /* USER CODE BEGIN adc */ + vdd-supply = <&vdd>; + vdda-supply = <&vdd>; + vref-supply = <&vrefbuf>; + + adc1:adc@0{ + st,min-sample-time-nsecs = <5000>; + st,adc-channels = <0 1 6 13 18 19>; + status = "okay"; + }; + + adc2:adc@100{ + st,adc-channels = <0 1 2 6 18 19>; + st,min-sample-time-nsecs = <5000>; + status = "okay"; + }; + /* USER CODE END adc */ +}; + +&bsec{ + status = "okay"; + + /* USER CODE BEGIN bsec */ + /* USER CODE END bsec */ +}; + +&cec{ + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&hdmi_cec_pins_mx>; + pinctrl-1 = <&hdmi_cec_sleep_pins_mx>; + status = "okay"; + + /* USER CODE BEGIN cec */ + /* USER CODE END cec */ +}; + +&crc1{ + status = "okay"; + + /* USER CODE BEGIN crc1 */ + /* USER CODE END crc1 */ +}; + +&cryp1{ + u-boot,dm-pre-reloc; + status = "okay"; + + /* USER CODE BEGIN cryp1 */ + /* USER CODE END cryp1 */ +}; + +&dma1{ + status = "okay"; + + /* USER CODE BEGIN dma1 */ + sram = <&dma_pool>; + /* USER CODE END dma1 */ +}; + +&dma2{ + status = "okay"; + + /* USER CODE BEGIN dma2 */ + sram = <&dma_pool>; + /* USER CODE END dma2 */ +}; + +&dmamux1{ + + dma-masters = <&dma1 &dma2>; + dma-channels = <16>; + + status = "okay"; + + /* USER CODE BEGIN dmamux1 */ + /* USER CODE END dmamux1 */ +}; + +&dts{ + status = "okay"; + + /* USER CODE BEGIN dts */ + /* USER CODE END dts */ +}; + +#if 1 + +ðernet0{ + pinctrl-names = "default", "sleep"; + pinctrl-0 = <ð1_pins_mx>; + pinctrl-1 = <ð1_sleep_pins_mx>; + status = "okay"; + + /* USER CODE BEGIN ethernet0 */ + phy-mode = "rgmii-id"; + max-speed = <1000>; + phy-handle = <&phy0>; + + mdio0{ + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dwmac-mdio"; + + phy0:ethernet-phy@0{ + reg = <0>; + }; + }; + /* USER CODE END ethernet0 */ +}; + +#endif + +&gpu{ + status = "disabled"; + + /* USER CODE BEGIN gpu */ + contiguous-area = <&gpu_reserved>; + /* USER CODE END gpu */ +}; + +&hash1{ + u-boot,dm-pre-reloc; + status = "okay"; + + /* USER CODE BEGIN hash1 */ + /* USER CODE END hash1 */ +}; + +&hsem{ + status = "okay"; + + /* USER CODE BEGIN hsem */ + /* USER CODE END hsem */ +}; + + + +&i2c1{ + u-boot,dm-pre-reloc; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&i2c1_pins_mx>; + pinctrl-1 = <&i2c1_sleep_pins_mx>; + status = "okay"; + + /* USER CODE BEGIN i2c1 */ + i2c-scl-rising-time-ns = <300>; + i2c-scl-falling-time-ns = <300>; + clock-frequency = <200000>; + /delete-property/ dmas; + /delete-property/ dma-names; + + /* Added by mirika @ SDT */ + /* STC 3115ST */ + /* fuel_gauge:stc3115@70 { + compatible = "st,stc3115"; + reg = <0x70>; + status = "okay"; + }; + */ + // leds:tlc59108@40 { + leds@0 { + compatible = "ti,tlc59108"; + reg=<0x40>; + #address-cells = <1>; + #size-cells =<0>; + status = "okay"; + + + ledA@0 { + label = "LedA-1"; + reg = <0x0>; + }; + ledA@1 { + label = "LedA-2"; + reg = <0x1>; + }; + ledA@2 { + label = "LedA-3"; + reg = <0x2>; + }; + ledA@3 { + label = "LedA-4"; + reg = <0x3>; + }; + }; + + leds@1 { + compatible = "ti,tlc59108"; + reg=<0x41>; + #address-cells = <1>; + #size-cells =<0>; + status = "okay"; + + + ledB@0 { + label = "LedB-1"; + reg = <0x0>; + }; + ledB@1 { + label = "LedB-2"; + reg = <0x1>; + }; + ledB@2 { + label = "LedB-3"; + reg = <0x2>; + }; + ledB@3 { + label = "LedB-4"; + reg = <0x3>; + }; + }; + + + + /* USER CODE END i2c1 */ +}; + +&i2c4{ + u-boot,dm-pre-reloc; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&i2c4_pins_z_mx>; + pinctrl-1 = <&i2c4_sleep_pins_z_mx>; + status = "okay"; + + /* USER CODE BEGIN i2c4 */ + i2c-scl-rising-time-ns = <185>; + i2c-scl-falling-time-ns = <20>; + clock-frequency = <400000>; + /delete-property/ dmas; + /delete-property/ dma-names; + + + + stusb1600@28{ + compatible = "st,stusb1600"; + reg = <0x28>; + interrupts = <11 IRQ_TYPE_EDGE_FALLING>; + interrupt-parent = <&gpioi>; + pinctrl-names = "default"; + pinctrl-0 = <&stusb1600_pins_a>; + status = "okay"; + vdd-supply = <&vin>; + + connector{ + compatible = "usb-c-connector"; + label = "USB-C"; + power-role = "dual"; + power-opmode = "default"; + + port{ + + con_usbotg_hs_ep:endpoint{ + remote-endpoint = <&usbotg_hs_ep>; + }; + }; + }; + }; + + pmic:stpmic@33{ + compatible = "st,stpmic1"; + reg = <0x33>; + interrupts-extended = <&exti_pwr 55 IRQ_TYPE_EDGE_FALLING>; + interrupt-controller; + #interrupt-cells = <2>; + status = "okay"; + + regulators{ + compatible = "st,stpmic1-regulators"; + buck1-supply = <&vin>; + buck2-supply = <&vin>; + buck3-supply = <&vin>; + buck4-supply = <&vin>; + ldo1-supply = <&v3v3>; + ldo2-supply = <&vin>; + ldo3-supply = <&vdd_ddr>; + ldo4-supply = <&vin>; + ldo5-supply = <&vin>; + ldo6-supply = <&v3v3>; + vref_ddr-supply = <&vin>; + boost-supply = <&vin>; + pwr_sw1-supply = <&bst_out>; + pwr_sw2-supply = <&bst_out>; + + vddcore:buck1{ + regulator-name = "vddcore"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1350000>; + regulator-always-on; + regulator-initial-mode = <0>; + regulator-over-current-protection; + }; + + vdd_ddr:buck2{ + regulator-name = "vdd_ddr"; + regulator-min-microvolt = <1350000>; + regulator-max-microvolt = <1350000>; + regulator-always-on; + regulator-initial-mode = <0>; + regulator-over-current-protection; + }; + + vdd:buck3{ + regulator-name = "vdd"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + st,mask-reset; + regulator-initial-mode = <0>; + regulator-over-current-protection; + }; + + v3v3:buck4{ + regulator-name = "v3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-over-current-protection; + regulator-initial-mode = <0>; + }; + + v1v8_audio:ldo1{ + regulator-name = "v1v8_audio"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + interrupts = ; + }; + + v3v3_hdmi:ldo2{ + regulator-name = "v3v3_hdmi"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + interrupts = ; + }; + + vtt_ddr:ldo3{ + regulator-name = "vtt_ddr"; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <750000>; + regulator-always-on; + regulator-over-current-protection; + }; + + vdd_usb:ldo4{ + regulator-name = "vdd_usb"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + interrupts = ; + regulator-always-on; + }; + + vdda:ldo5{ + regulator-name = "vdda"; + regulator-min-microvolt = <2900000>; + regulator-max-microvolt = <2900000>; + interrupts = ; + regulator-boot-on; + }; + + v1v2_hdmi:ldo6{ + regulator-name = "v1v2_hdmi"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + interrupts = ; + }; + + vref_ddr:vref_ddr{ + regulator-name = "vref_ddr"; + regulator-always-on; + regulator-over-current-protection; + }; + + bst_out:boost{ + regulator-name = "bst_out"; + interrupts = ; + }; + + vbus_otg:pwr_sw1{ + regulator-name = "vbus_otg"; + interrupts = ; + }; + + vbus_sw:pwr_sw2{ + regulator-name = "vbus_sw"; + interrupts = ; + regulator-active-discharge = <1>; + }; + }; + + onkey{ + compatible = "st,stpmic1-onkey"; + interrupts = , ; + interrupt-names = "onkey-falling", "onkey-rising"; + power-off-time-sec = <10>; + status = "okay"; + }; + + watchdog { + compatible = "st,stpmic1-wdt"; + status = "disabled"; + }; + }; + /* USER CODE END i2c4 */ +}; + +&i2s2{ + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&i2s2_pins_mx>; + pinctrl-1 = <&i2s2_sleep_pins_mx>; + status = "okay"; + + /* USER CODE BEGIN i2s2 */ + clocks = <&rcc SPI2>, <&rcc SPI2_K>, <&rcc PLL3_Q>, <&rcc PLL3_R>; + clock-names = "pclk", "i2sclk", "x8k", "x11k"; + /* USER CODE END i2s2 */ +}; + +&ipcc{ + status = "okay"; + + /* USER CODE BEGIN ipcc */ + /* USER CODE END ipcc */ +}; + +&iwdg2{ + status = "okay"; + + /* USER CODE BEGIN iwdg2 */ + timeout-sec = <32>; + /* USER CODE END iwdg2 */ +}; + +&mdma1{ + status = "okay"; + + /* USER CODE BEGIN mdma1 */ + /* USER CODE END mdma1 */ +}; + +&pwr_regulators{ + status = "okay"; + + /* USER CODE BEGIN pwr_regulators */ + vdd-supply = <&vdd>; + vdd_3v3_usbfs-supply = <&vdd_usb>; + /* USER CODE END pwr_regulators */ +}; + +&rcc{ + u-boot,dm-pre-reloc; + status = "okay"; + + /* USER CODE BEGIN rcc */ + /* USER CODE END rcc */ +}; + +&rng1{ + status = "okay"; + + /* USER CODE BEGIN rng1 */ + /* USER CODE END rng1 */ +}; + +&rtc{ + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&rtc_pins_mx>; + pinctrl-1 = <&rtc_sleep_pins_mx>; + status = "okay"; + + /* USER CODE BEGIN rtc */ + st,lsco = ; + /* USER CODE END rtc */ +}; + +#if 0 + +#if IECN_SPI5_MAX3109_A7_LINUX +#else +/* IECN I/F #2 SPI5 */ +#endif + +#endif + +#if 1 +&gpioh { + interrupt-controller; +}; +#endif + +#if IECN_SPI1_MAX3109_A7_LINUX +/** +* Author : dongmin.kim@sdt (Kimdongmin-sdt) +*/ +&spi1 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&spi1_pins_z_mx>; + pinctrl-1 = <&spi1_sleep_pins_z_mx>; + cs-gpios = <&gpioz 3 0>; + status = "okay"; + + max3109@44004000{ + compatible = "maxim,max3109"; + reg = <0>; + clocks = <&spi_uart_clk 0>; + clocks-names = "osc"; + spi-max-frequency = <4000000>; + #address-cells = <1>; + #size-cells=<0>; + interrupt-parent = <&gpioh>; /* irq4 -> PH15 */ + interrupts = <15 IRQ_TYPE_EDGE_FALLING>; + status="disable"; + }; + // spidev@0{ + // status="okay"; + // compatible = "rohm,dh2228fv", "linux,spidev"; + // reg = <0>; + // // reg = <0x44004000 0x3ff>; + // spi-max-frequency = <4000000>; + // }; +}; +// &spi1{ +// pinctrl-names = "default", "sleep"; +// pinctrl-0 = <&spi1_pins_z_mx>; +// pinctrl-1 = <&spi1_sleep_pins_z_mx>; +// cs-gpios = <&gpioz 3 0>; +// #address-cells = <1>; +// #size-cells = <1>; +// status = "okay"; +// /* SDT_NodeQ driver */ +// ads131e08@44004000{ +// compatible = "ti", "ads131e08"; +// reg = <0x44004000 0x3ff>; +// spi-max-frequency = <10000000>; +// status="okay"; +// clocks = <&spi_uart_clk 0>; +// clocks-names = "osc"; +// interrupt-parent = <&gpioh>; /* irq4 -> PH15 */ +// interrupts = <15 IRQ_TYPE_EDGE_FALLING>; +// }; +// }; +// &spi1{ +// pinctrl-names = "default", "sleep"; +// pinctrl-0 = <&spi1_pins_z_mx>; +// pinctrl-1 = <&spi1_sleep_pins_z_mx>; +// cs-gpios = <&gpioz 3 0>; +// #address-cells = <1>; +// #size-cells = <1>; +// status = "okay"; +// /* SDT_NodeQ driver */ +// SDT_NodeQ@44004000{ +// compatible = "pisosr-gpio", "maxim,max3109"; +// reg = <0x44004000 0x3ff>; +// spi-max-frequency = <10000000>; +// status="okay"; +// clocks = <&spi_uart_clk 0>; +// clocks-names = "osc"; +// interrupt-parent = <&gpioh>; /* irq4 -> PH15 */ +// interrupts = <15 IRQ_TYPE_EDGE_FALLING>; +// }; +// }; + +&spi5{ + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&spi5_pins_mx>; + pinctrl-1 = <&spi5_sleep_pins_mx>; + cs-gpios = <&gpiof 6 0>; + status = "okay"; + #address-cells = <1>; + #size-cells = <1>; + /* SDT_NodeQ driver */ + SDT_NodeQ@44009000{ + compatible = "maxim,max3109"; + reg = <0>; + clocks = <&spi_uart_clk 0>; + clocks-names = "osc"; + spi-max-frequency = <10000000>; + #address-cells = <1>; + #size-cells=<0>; + + interrupt-parent = <&gpioh>; /* irq5 -> PH6 */ + interrupts = <6 IRQ_TYPE_EDGE_FALLING>; + }; +}; + +#else + +#endif + +&tamp{ + status = "okay"; + + /* USER CODE BEGIN tamp */ + /* USER CODE END tamp */ +}; + + + +&uart4{ + u-boot,dm-pre-reloc; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&uart4_pins_mx>; + pinctrl-1 = <&uart4_sleep_pins_mx>; + status = "okay"; + + /* USER CODE BEGIN uart4 */ + /delete-property/ dmas; + /delete-property/ dma-names; + /* USER CODE END uart4 */ +}; + + +&usart2{ + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&usart2_pins_mx>; + pinctrl-1 = <&usart2_sleep_pins_mx>; + status = "okay"; + + /* USER CODE BEGIN usart2 */ + uart-has-rtscts; +}; + +&usbh_ehci{ + status = "okay"; + + /* USER CODE BEGIN usbh_ehci */ + phys = <&usbphyc_port0>; + /* USER CODE END usbh_ehci */ +}; + +&usbh_ohci{ + status = "okay"; + + /* USER CODE BEGIN usbh_ohci */ + /* USER CODE END usbh_ohci */ +}; + +&usbotg_hs{ + u-boot,dm-pre-reloc; + status = "okay"; + + /* USER CODE BEGIN usbotg_hs */ + phys = <&usbphyc_port1 0>; + phy-names = "usb2-phy"; + usb-role-switch; + + port{ + + usbotg_hs_ep:endpoint{ + remote-endpoint = <&con_usbotg_hs_ep>; + }; + }; + /* USER CODE END usbotg_hs */ +}; + +&usbphyc{ + u-boot,dm-pre-reloc; + status = "okay"; + + /* USER CODE BEGIN usbphyc */ + /* USER CODE END usbphyc */ +}; + +&usbphyc_port0{ + u-boot,dm-pre-reloc; + status = "okay"; + + /* USER CODE BEGIN usbphyc_port0 */ + phy-supply = <&vdd_usb>; + st,phy-tuning = <&usb_phy_tuning>; + /* USER CODE END usbphyc_port0 */ +}; + +&usbphyc_port1{ + u-boot,dm-pre-reloc; + status = "okay"; + + /* USER CODE BEGIN usbphyc_port1 */ + phy-supply = <&vdd_usb>; + st,phy-tuning = <&usb_phy_tuning>; + /* USER CODE END usbphyc_port1 */ +}; + +&vrefbuf{ + status = "okay"; + + /* USER CODE BEGIN vrefbuf */ + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + vdda-supply = <&vdd>; + /* USER CODE END vrefbuf */ +}; + +/* USER CODE BEGIN addons */ +&adc { + status = "disabled"; +}; + +&usbh_ohci{ + phys = <&usbphyc_port0>; +}; + +&cpu0{ + cpu-supply = <&vddcore>; +}; + +&cpu1{ + cpu-supply = <&vddcore>; +}; + +&sram{ + + dma_pool:dma_pool@0{ + reg = <0x50000 0x10000>; + pool; + }; +}; + +// Added by SDT +&m_can1{ + pinctrl-names = "default"; + pinctrl-0 = <&fdcan1_pins_mx>; + pinctrl-1 = <&fdcan1_sleep_pins_mx>; + status = "okay"; + + /* USER CODE BEGIN m_can1 */ + /* USER CODE END m_can1 */ +}; + +&m_can2{ + pinctrl-names = "default"; + pinctrl-0 = <&fdcan2_pins_mx>; + pinctrl-1 = <&fdcan2_sleep_pins_mx>; + status = "okay"; + + /* USER CODE BEGIN m_can1 */ + /* USER CODE END m_can1 */ +}; + +/* SD-CARD */ +&sdmmc1{ + u-boot,dm-pre-reloc; + pinctrl-names = "default", "opendrain", "sleep"; + pinctrl-0 = <&sdmmc1_pins_mx>; + pinctrl-1 = <&sdmmc1_opendrain_pins_mx>; + pinctrl-2 = <&sdmmc1_sleep_pins_mx>; + status = "okay"; + + /* USER CODE BEGIN sdmmc1 */ + cd-gpios = <&gpiob 7 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; + disable-wp; + st,neg-edge; + bus-width = <4>; + vmmc-supply = <&v3v3>; + /* USER CODE END sdmmc1 */ +}; + +/* eMMC */ +&sdmmc2 { + pinctrl-names = "default","opendrain","sleep"; + pinctrl-0 = <&sdmmc2_pins_mx>; + pinctrl-1 = <&sdmmc2_opendrain_pins_mx>; + pinctrl-2 = <&sdmmc2_sleep_pins_mx>; + non-removable; + no-sd; + no-sdio; + st,neg-edge; + bus-width = <4>; //bus-width 4 사용이면 4로 변경 + vmmc-supply = <&v3v3>; + vqmmc-supply = <&vdd>; + mmc-ddr-3_3v; + status = "okay"; +}; + +/* USER CODE END addons */ diff --git a/meta-st/meta-st-stm32mpu-hce/mx/STM32MP157C-DK2/DeviceTree/hce/tf-a/stm32mp15-mx.dtsi b/meta-st/meta-st-stm32mpu-hce/mx/STM32MP157C-DK2/DeviceTree/hce/tf-a/stm32mp15-mx.dtsi new file mode 100755 index 0000000..48f1e41 --- /dev/null +++ b/meta-st/meta-st-stm32mpu-hce/mx/STM32MP157C-DK2/DeviceTree/hce/tf-a/stm32mp15-mx.dtsi @@ -0,0 +1,240 @@ +/* + * Copyright (C) 2015-2018, STMicroelectronics - All Rights Reserved + * + * SPDX-License-Identifier: GPL-2.0+ BSD-3-Clause + * + */ + + #ifdef DDR_N_1GB + +/* + * File generated by STMicroelectronics STM32CubeMX DDR Tool for MPUs + * DDR type: DDR3 / DDR3L + * DDR width: 16bits + * DDR density: 4Gb + * System frequency: 533000Khz + * Relaxed Timing Mode: false + * Address mapping type: RBC + * + * Save Date: 2020.06.30, save Time: 17:39:59 + */ + +#define DDR_MEM_NAME "DDR3-DDR3L 16bits 533000Khz" +#define DDR_MEM_SPEED 533000 +#define DDR_MEM_SIZE 0x20000000 + +#define DDR_MSTR 0x00041401 +#define DDR_MRCTRL0 0x00000010 +#define DDR_MRCTRL1 0x00000000 +#define DDR_DERATEEN 0x00000000 +#define DDR_DERATEINT 0x00800000 +#define DDR_PWRCTL 0x00000000 +#define DDR_PWRTMG 0x00400010 +#define DDR_HWLPCTL 0x00000000 +#define DDR_RFSHCTL0 0x00210000 +#define DDR_RFSHCTL3 0x00000000 +#define DDR_RFSHTMG 0x0081008B +#define DDR_CRCPARCTL0 0x00000000 +#define DDR_DRAMTMG0 0x121B2414 +#define DDR_DRAMTMG1 0x000A041C +#define DDR_DRAMTMG2 0x0608090F +#define DDR_DRAMTMG3 0x0050400C +#define DDR_DRAMTMG4 0x08040608 +#define DDR_DRAMTMG5 0x06060403 +#define DDR_DRAMTMG6 0x02020002 +#define DDR_DRAMTMG7 0x00000202 +#define DDR_DRAMTMG8 0x00001005 +#define DDR_DRAMTMG14 0x000000A0 +#define DDR_ZQCTL0 0xC2000040 +#define DDR_DFITMG0 0x02060105 +#define DDR_DFITMG1 0x00000202 +#define DDR_DFILPCFG0 0x07000000 +#define DDR_DFIUPD0 0xC0400003 +#define DDR_DFIUPD1 0x00000000 +#define DDR_DFIUPD2 0x00000000 +#define DDR_DFIPHYMSTR 0x00000000 +#define DDR_ODTCFG 0x06000600 +#define DDR_ODTMAP 0x00000001 +#define DDR_SCHED 0x00000C01 +#define DDR_SCHED1 0x00000000 +#define DDR_PERFHPR1 0x01000001 +#define DDR_PERFLPR1 0x08000200 +#define DDR_PERFWR1 0x08000400 +#define DDR_DBG0 0x00000000 +#define DDR_DBG1 0x00000000 +#define DDR_DBGCMD 0x00000000 +#define DDR_POISONCFG 0x00000000 +#define DDR_PCCFG 0x00000010 +#define DDR_PCFGR_0 0x00010000 +#define DDR_PCFGW_0 0x00000000 +#define DDR_PCFGQOS0_0 0x02100C03 +#define DDR_PCFGQOS1_0 0x00800100 +#define DDR_PCFGWQOS0_0 0x01100C03 +#define DDR_PCFGWQOS1_0 0x01000200 +#define DDR_PCFGR_1 0x00010000 +#define DDR_PCFGW_1 0x00000000 +#define DDR_PCFGQOS0_1 0x02100C03 +#define DDR_PCFGQOS1_1 0x00800040 +#define DDR_PCFGWQOS0_1 0x01100C03 +#define DDR_PCFGWQOS1_1 0x01000200 +#define DDR_ADDRMAP1 0x00070707 +#define DDR_ADDRMAP2 0x00000000 +#define DDR_ADDRMAP3 0x1F000000 +#define DDR_ADDRMAP4 0x00001F1F +#define DDR_ADDRMAP5 0x06060606 +#define DDR_ADDRMAP6 0x0F060606 +#define DDR_ADDRMAP9 0x00000000 +#define DDR_ADDRMAP10 0x00000000 +#define DDR_ADDRMAP11 0x00000000 +#define DDR_PGCR 0x01442E02 +#define DDR_PTR0 0x0022AA5B +#define DDR_PTR1 0x04841104 +#define DDR_PTR2 0x042DA068 +#define DDR_ACIOCR 0x10400812 +#define DDR_DXCCR 0x00000C40 +#define DDR_DSGCR 0xF200011F +#define DDR_DCR 0x0000000B +#define DDR_DTPR0 0x38D488D0 +#define DDR_DTPR1 0x098B00D8 +#define DDR_DTPR2 0x10023600 +#define DDR_MR0 0x00000840 +#define DDR_MR1 0x00000000 +#define DDR_MR2 0x00000208 +#define DDR_MR3 0x00000000 +#define DDR_ODTCR 0x00010000 +#define DDR_ZQ0CR1 0x00000038 +#define DDR_DX0GCR 0x0000CE81 +#define DDR_DX0DLLCR 0x40000000 +#define DDR_DX0DQTR 0xFFFFFFFF +#define DDR_DX0DQSTR 0x3DB02000 +#define DDR_DX1GCR 0x0000CE81 +#define DDR_DX1DLLCR 0x40000000 +#define DDR_DX1DQTR 0xFFFFFFFF +#define DDR_DX1DQSTR 0x3DB02000 +#define DDR_DX2GCR 0x0000CE80 +#define DDR_DX2DLLCR 0x40000000 +#define DDR_DX2DQTR 0xFFFFFFFF +#define DDR_DX2DQSTR 0x3DB02000 +#define DDR_DX3GCR 0x0000CE80 +#define DDR_DX3DLLCR 0x40000000 +#define DDR_DX3DQTR 0xFFFFFFFF +#define DDR_DX3DQSTR 0x3DB02000 + + +#else + + +/* + * File generated by STMicroelectronics STM32CubeMX DDR Tool for MPUs + * DDR type: DDR3 / DDR3L + * DDR width: 16bits + * DDR density: 8Gb + * System frequency: 533000Khz + * Relaxed Timing Mode: false + * Address mapping type: RBC + * + * Save Date: 2021.03.15, save Time: 14:30:04 + */ + +#define DDR_MEM_NAME "DDR3-DDR3L 16bits 533000Khz" +#define DDR_MEM_SPEED 533000 +#define DDR_MEM_SIZE 0x40000000 + +#define DDR_MSTR 0x00041401 +#define DDR_MRCTRL0 0x00000010 +#define DDR_MRCTRL1 0x00000000 +#define DDR_DERATEEN 0x00000000 +#define DDR_DERATEINT 0x00800000 +#define DDR_PWRCTL 0x00000000 +#define DDR_PWRTMG 0x00400010 +#define DDR_HWLPCTL 0x00000000 +#define DDR_RFSHCTL0 0x00210000 +#define DDR_RFSHCTL3 0x00000000 +#define DDR_RFSHTMG 0x0081008B +#define DDR_CRCPARCTL0 0x00000000 +#define DDR_DRAMTMG0 0x121B2414 +#define DDR_DRAMTMG1 0x000A041C +#define DDR_DRAMTMG2 0x0608090F +#define DDR_DRAMTMG3 0x0050400C +#define DDR_DRAMTMG4 0x08040608 +#define DDR_DRAMTMG5 0x06060403 +#define DDR_DRAMTMG6 0x02020002 +#define DDR_DRAMTMG7 0x00000202 +#define DDR_DRAMTMG8 0x00001005 +#define DDR_DRAMTMG14 0x000000A0 +#define DDR_ZQCTL0 0xC2000040 +#define DDR_DFITMG0 0x02060105 +#define DDR_DFITMG1 0x00000202 +#define DDR_DFILPCFG0 0x07000000 +#define DDR_DFIUPD0 0xC0400003 +#define DDR_DFIUPD1 0x00000000 +#define DDR_DFIUPD2 0x00000000 +#define DDR_DFIPHYMSTR 0x00000000 +#define DDR_ODTCFG 0x06000600 +#define DDR_ODTMAP 0x00000001 +#define DDR_SCHED 0x00000C01 +#define DDR_SCHED1 0x00000000 +#define DDR_PERFHPR1 0x01000001 +#define DDR_PERFLPR1 0x08000200 +#define DDR_PERFWR1 0x08000400 +#define DDR_DBG0 0x00000000 +#define DDR_DBG1 0x00000000 +#define DDR_DBGCMD 0x00000000 +#define DDR_POISONCFG 0x00000000 +#define DDR_PCCFG 0x00000010 +#define DDR_PCFGR_0 0x00010000 +#define DDR_PCFGW_0 0x00000000 +#define DDR_PCFGQOS0_0 0x02100C03 +#define DDR_PCFGQOS1_0 0x00800100 +#define DDR_PCFGWQOS0_0 0x01100C03 +#define DDR_PCFGWQOS1_0 0x01000200 +#define DDR_PCFGR_1 0x00010000 +#define DDR_PCFGW_1 0x00000000 +#define DDR_PCFGQOS0_1 0x02100C03 +#define DDR_PCFGQOS1_1 0x00800040 +#define DDR_PCFGWQOS0_1 0x01100C03 +#define DDR_PCFGWQOS1_1 0x01000200 +#define DDR_ADDRMAP1 0x00070707 +#define DDR_ADDRMAP2 0x00000000 +#define DDR_ADDRMAP3 0x1F000000 +#define DDR_ADDRMAP4 0x00001F1F +#define DDR_ADDRMAP5 0x06060606 +#define DDR_ADDRMAP6 0x06060606 +#define DDR_ADDRMAP9 0x00000000 +#define DDR_ADDRMAP10 0x00000000 +#define DDR_ADDRMAP11 0x00000000 +#define DDR_PGCR 0x01442E02 +#define DDR_PTR0 0x0022AA5B +#define DDR_PTR1 0x04841104 +#define DDR_PTR2 0x042DA068 +#define DDR_ACIOCR 0x10400812 +#define DDR_DXCCR 0x00000C40 +#define DDR_DSGCR 0xF200011F +#define DDR_DCR 0x0000000B +#define DDR_DTPR0 0x38D488D0 +#define DDR_DTPR1 0x098B00D8 +#define DDR_DTPR2 0x10023600 +#define DDR_MR0 0x00000840 +#define DDR_MR1 0x00000000 +#define DDR_MR2 0x00000208 +#define DDR_MR3 0x00000000 +#define DDR_ODTCR 0x00010000 +#define DDR_ZQ0CR1 0x00000038 +#define DDR_DX0GCR 0x0000CE81 +#define DDR_DX0DLLCR 0x40000000 +#define DDR_DX0DQTR 0x33333333 +#define DDR_DX0DQSTR 0x3DB02000 +#define DDR_DX1GCR 0x0000CE81 +#define DDR_DX1DLLCR 0x40000000 +#define DDR_DX1DQTR 0x33333333 +#define DDR_DX1DQSTR 0x3DB02000 +#define DDR_DX2GCR 0x0000CE80 +#define DDR_DX2DLLCR 0x40000000 +#define DDR_DX2DQTR 0xFFFFFFFF +#define DDR_DX2DQSTR 0x3DB02000 +#define DDR_DX3GCR 0x0000CE80 +#define DDR_DX3DLLCR 0x40000000 +#define DDR_DX3DQTR 0xFFFFFFFF +#define DDR_DX3DQSTR 0x3DB02000 + +#endif \ No newline at end of file diff --git a/meta-st/meta-st-stm32mpu-hce/mx/STM32MP157C-DK2/DeviceTree/hce/tf-a/stm32mp157c-hce-mx.dts b/meta-st/meta-st-stm32mpu-hce/mx/STM32MP157C-DK2/DeviceTree/hce/tf-a/stm32mp157c-hce-mx.dts new file mode 100644 index 0000000..3dcdc09 --- /dev/null +++ b/meta-st/meta-st-stm32mpu-hce/mx/STM32MP157C-DK2/DeviceTree/hce/tf-a/stm32mp157c-hce-mx.dts @@ -0,0 +1,784 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */ +/* + * Copyright (C) STMicroelectronics 2020 - All Rights Reserved + * Author: STM32CubeMX code generation for STMicroelectronics. + */ + +/* For more information on Device Tree configuration, please refer to + * https://wiki.st.com/stm32mpu/wiki/Category:Device_tree_configuration + */ + +/dts-v1/; +#include +#include +#include +#include "stm32mp15-mx.dtsi" + +#include "stm32mp157.dtsi" +#include "stm32mp15xc.dtsi" +#include "stm32mp15xxac-pinctrl.dtsi" +#include "stm32mp15-ddr.dtsi" + +/* USER CODE BEGIN includes */ +#include +/* USER CODE END includes */ + +/ { + model = "STMicroelectronics STM32MP157C-DK2 STM32CubeMX board"; + compatible = "st,stm32mp157c-hce-mx", "st,stm32mp157"; + + /* USER CODE BEGIN root */ + + memory@c0000000{ + device_type = "memory"; + reg = <0xc0000000 0x20000000>; + }; + + vin:vin{ + compatible = "regulator-fixed"; + regulator-name = "vin"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + }; + + aliases{ + serial0 = &uart4; + serial1 = &usart3; + serial2 = &uart7; + serial3 = &usart2; + // by mirika + mmc0 = &sdmmc1; + mmc1 = &sdmmc2; + }; + + chosen{ + stdout-path = "serial0:115200n8"; + }; + /* USER CODE END root */ + + clocks { + + /* USER CODE BEGIN clocks */ + /* USER CODE END clocks */ + + clk_lse: clk-lse { + st,drive = < LSEDRV_MEDIUM_HIGH >; + + /* USER CODE BEGIN clk_lse */ + /* USER CODE END clk_lse */ + }; + + clk_hse: clk-hse { + st,digbypass; + + /* USER CODE BEGIN clk_hse */ + /* USER CODE END clk_hse */ + }; + }; + +}; /*root*/ + +&pinctrl { + rtc_pins_mx: rtc_mx-0 { + pins { + pinmux = ; /* RTC_LSCO */ + }; + }; + + sdmmc1_pins_mx: sdmmc1_mx-0 { + pins1 { + pinmux = , /* SDMMC1_D0 */ + , /* SDMMC1_D1 */ + , /* SDMMC1_D2 */ + , /* SDMMC1_D3 */ + ; /* SDMMC1_CMD */ + bias-disable; + drive-push-pull; + slew-rate = <1>; + }; + pins2 { + pinmux = ; /* SDMMC1_CK */ + bias-disable; + drive-push-pull; + slew-rate = <2>; + }; + }; + + sdmmc2_pins_mx: sdmmc2_mx-0 { + pins1 { + pinmux = , /* SDMMC2_D0 */ + , /* SDMMC2_D1 */ + , /* SDMMC2_D2 */ + , /* SDMMC2_D3 */ + ; /* SDMMC2_CMD */ + slew-rate = <1>; + drive-push-pull; + bias-pull-up; + }; + pins2 { + pinmux = ; /* SDMMC2_CK */ + slew-rate = <2>; + drive-push-pull; + bias-pull-up; + }; + }; + + sdmmc2_opendrain_pins_mx: sdmmc2_opendrain_mx-0 { + pins1 { + pinmux = , /* SDMMC2_D2 */ + , /* SDMMC2_D3 */ + , /* SDMMC2_D0 */ + ; /* SDMMC2_D1 */ + bias-disable; + drive-push-pull; + slew-rate = <1>; + }; + pins2 { + pinmux = ; /* SDMMC2_CK */ + bias-disable; + drive-push-pull; + slew-rate = <2>; + }; + pins3 { + pinmux = ; /* SDMMC2_CMD */ + bias-disable; + drive-open-drain; + slew-rate = <1>; + }; + }; + + sdmmc2_sleep_pins_mx: sdmmc2_sleep_mx-0 { + pins { + pinmux = , /* SDMMC2_D2 */ + , /* SDMMC2_D3 */ + , /* SDMMC2_D0 */ + , /* SDMMC2_D1 */ + , /* SDMMC2_CK */ + ; /* SDMMC2_CMD */ + }; + }; + + + uart4_pins_mx: uart4_mx-0 { + pins1 { + pinmux = ; /* UART4_RX */ + bias-disable; + }; + pins2 { + pinmux = ; /* UART4_TX */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + }; + + /* USER CODE BEGIN pinctrl */ + /* USER CODE END pinctrl */ +}; + +&pinctrl_z { + i2c4_pins_z_mx: i2c4_mx-0 { + pins { + pinmux = , /* I2C4_SCL */ + ; /* I2C4_SDA */ + bias-disable; + drive-open-drain; + slew-rate = <0>; + }; + }; + + /* USER CODE BEGIN pinctrl_z */ + /* USER CODE END pinctrl_z */ +}; + +&rcc { + st,csi-cal; + st,hsi-cal; + st,cal-sec = <60>; + st,clksrc = < + CLK_MPU_PLL1P + CLK_AXI_PLL2P + CLK_MCU_PLL3P + CLK_PLL12_HSE + CLK_PLL3_HSE + CLK_PLL4_HSE + CLK_RTC_LSE + CLK_MCO1_DISABLED + CLK_MCO2_DISABLED + >; + st,clkdiv = < + 1 /*MPU*/ + 0 /*AXI*/ + 0 /*MCU*/ + 1 /*APB1*/ + 1 /*APB2*/ + 1 /*APB3*/ + 1 /*APB4*/ + 2 /*APB5*/ + 23 /*RTC*/ + 0 /*MCO1*/ + 0 /*MCO2*/ + >; + st,pkcs = < + CLK_CKPER_HSE + CLK_ETH_DISABLED + CLK_SDMMC12_PLL4P + CLK_DSI_DSIPLL + CLK_STGEN_HSE + CLK_USBPHY_HSE + CLK_SPI2S1_DISABLED + CLK_SPI2S23_PLL3Q + CLK_SPI45_PCLK2 + CLK_SPI6_DISABLED + CLK_I2C46_HSI + CLK_SDMMC3_PLL4P + CLK_USBO_USBPHY + CLK_ADC_CKPER + CLK_CEC_LSE + CLK_I2C12_HSI + CLK_I2C35_DISABLED + CLK_UART1_DISABLED + CLK_UART24_HSI + CLK_UART35_HSI + CLK_UART6_DISABLED + CLK_UART78_DISABLED + CLK_SPDIF_DISABLED + CLK_FDCAN_HSE + CLK_SAI1_DISABLED + CLK_SAI2_DISABLED + CLK_SAI3_DISABLED + CLK_SAI4_DISABLED + CLK_RNG1_LSI + CLK_LPTIM1_DISABLED + CLK_LPTIM23_DISABLED + CLK_LPTIM45_DISABLED + + >; + #if 0 + /* Added by SDK */ + /* pll 411Mhz */ + pll1:st,pll@0 { + cfg = < 1 33 0 1 1 PQR(1,0,0) >; + frac = < 0x800 >; + }; + /* */ + #endif + + pll2:st,pll@1 { + compatible = "st,stm32mp1-pll"; + reg = <1>; + cfg = < 2 65 1 0 0 PQR(1,1,1) >; + frac = < 0x1400 >; + }; + pll3:st,pll@2 { + compatible = "st,stm32mp1-pll"; + reg = <2>; + cfg = < 1 33 1 16 36 PQR(1,1,0) >; + frac = < 0x1a04 >; + }; + pll4:st,pll@3 { + compatible = "st,stm32mp1-pll"; + reg = <3>; + cfg = < 3 98 5 7 7 PQR(1,1,0) >; + }; +}; + +&bsec{ + status = "okay"; + secure-status = "okay"; + + /* USER CODE BEGIN bsec */ + + board_id:board_id@ec{ + reg = <0xec 0x4>; + st,non-secure-otp; + }; + /* USER CODE END bsec */ +}; + +&cryp1{ + status = "okay"; + + /* USER CODE BEGIN cryp1 */ + /* USER CODE END cryp1 */ +}; + +&etzpc{ + st,decprot = < + /*"Non Secured" peripherals*/ + DECPROT(STM32MP1_ETZPC_ADC_ID, DECPROT_NS_RW, DECPROT_UNLOCK) + DECPROT(STM32MP1_ETZPC_CRYP1_ID, DECPROT_NS_RW, DECPROT_UNLOCK) + DECPROT(STM32MP1_ETZPC_DMA1_ID, DECPROT_NS_RW, DECPROT_UNLOCK) + DECPROT(STM32MP1_ETZPC_DMA2_ID, DECPROT_NS_RW, DECPROT_UNLOCK) + DECPROT(STM32MP1_ETZPC_DMAMUX_ID, DECPROT_NS_RW, DECPROT_UNLOCK) + DECPROT(STM32MP1_ETZPC_ETH_ID, DECPROT_NS_RW, DECPROT_UNLOCK) + DECPROT(STM32MP1_ETZPC_HASH1_ID, DECPROT_NS_RW, DECPROT_UNLOCK) + DECPROT(STM32MP1_ETZPC_CEC_ID, DECPROT_NS_RW, DECPROT_UNLOCK) + DECPROT(STM32MP1_ETZPC_I2C1_ID, DECPROT_NS_RW, DECPROT_UNLOCK) + DECPROT(STM32MP1_ETZPC_I2C4_ID, DECPROT_NS_RW, DECPROT_UNLOCK) + DECPROT(STM32MP1_ETZPC_SPI2_ID, DECPROT_NS_RW, DECPROT_UNLOCK) + DECPROT(STM32MP1_ETZPC_RNG1_ID, DECPROT_NS_RW, DECPROT_UNLOCK) + DECPROT(STM32MP1_ETZPC_SAI2_ID, DECPROT_NS_RW, DECPROT_UNLOCK) + DECPROT(STM32MP1_ETZPC_SPI5_ID, DECPROT_NS_RW, DECPROT_UNLOCK) + DECPROT(STM32MP1_ETZPC_UART4_ID, DECPROT_NS_RW, DECPROT_UNLOCK) + DECPROT(STM32MP1_ETZPC_USART2_ID, DECPROT_NS_RW, DECPROT_UNLOCK) + DECPROT(STM32MP1_ETZPC_OTG_ID, DECPROT_NS_RW, DECPROT_UNLOCK) + DECPROT(STM32MP1_ETZPC_VREFBUF_ID, DECPROT_NS_RW, DECPROT_UNLOCK) + /*"Secured" peripherals*/ + DECPROT(STM32MP1_ETZPC_DDRCTRL_ID, DECPROT_S_RW, DECPROT_UNLOCK) + DECPROT(STM32MP1_ETZPC_DDRPHYC_ID, DECPROT_S_RW, DECPROT_UNLOCK) + DECPROT(STM32MP1_ETZPC_STGENC_ID, DECPROT_S_RW, DECPROT_UNLOCK) + + /*Restriction: following IDs are not managed - please to use User-Section if needed: + STM32MP1_ETZPC_SRAMx_ID, STM32MP1_ETZPC_RETRAM_ID, STM32MP1_ETZPC_BKPSRAM_ID*/ + + /* USER CODE BEGIN etzpc_decprot */ + /*STM32CubeMX generates a basic and standard configuration for ETZPC. + Additional device configurations can be added here if needed. + "etzpc" node could be also overloaded in "addons" User-Section.*/ + + DECPROT(STM32MP1_ETZPC_BKPSRAM_ID, DECPROT_S_RW, DECPROT_UNLOCK) + + /* USER CODE END etzpc_decprot */ + >; + + secure-status = "okay"; + + /* USER CODE BEGIN etzpc */ + /* USER CODE END etzpc */ +}; + +&hash1{ + status = "okay"; + + /* USER CODE BEGIN hash1 */ + /* USER CODE END hash1 */ +}; + +&i2c4{ + pinctrl-names = "default"; + pinctrl-0 = <&i2c4_pins_z_mx>; + status = "okay"; + secure-status = "okay"; + + /* USER CODE BEGIN i2c4 */ + i2c-scl-rising-time-ns = <185>; + i2c-scl-falling-time-ns = <20>; + clock-frequency = <400000>; + + pmic:stpmic@33{ + compatible = "st,stpmic1"; + reg = <0x33>; + interrupts-extended = <&exti_pwr 55 IRQ_TYPE_EDGE_FALLING>; + interrupt-controller; + #interrupt-cells = <2>; + status = "okay"; + + regulators{ + compatible = "st,stpmic1-regulators"; + buck1-supply = <&vin>; + buck2-supply = <&vin>; + buck3-supply = <&vin>; + buck4-supply = <&vin>; + ldo1-supply = <&v3v3>; + ldo2-supply = <&vin>; + ldo3-supply = <&vdd_ddr>; + ldo4-supply = <&vin>; + ldo5-supply = <&vin>; + ldo6-supply = <&v3v3>; + vref_ddr-supply = <&vin>; + boost-supply = <&vin>; + pwr_sw1-supply = <&bst_out>; + pwr_sw2-supply = <&bst_out>; + + vddcore:buck1{ + regulator-name = "vddcore"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1350000>; + regulator-always-on; + regulator-initial-mode = <0>; + regulator-over-current-protection; + + lp-stop{ + regulator-on-in-suspend; + regulator-suspend-microvolt = <1200000>; + }; + + standby-ddr-sr{ + regulator-off-in-suspend; + }; + + standby-ddr-off{ + regulator-off-in-suspend; + }; + }; + + vdd_ddr:buck2{ + regulator-name = "vdd_ddr"; + regulator-min-microvolt = <1350000>; + regulator-max-microvolt = <1350000>; + regulator-always-on; + regulator-initial-mode = <0>; + regulator-over-current-protection; + + lp-stop{ + regulator-suspend-microvolt = <1350000>; + regulator-on-in-suspend; + }; + + standby-ddr-sr{ + regulator-suspend-microvolt = <1350000>; + regulator-on-in-suspend; + }; + + standby-ddr-off{ + regulator-off-in-suspend; + }; + }; + + vdd:buck3{ + regulator-name = "vdd"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + st,mask-reset; + regulator-initial-mode = <0>; + regulator-over-current-protection; + + lp-stop{ + regulator-suspend-microvolt = <3300000>; + regulator-on-in-suspend; + }; + + standby-ddr-sr{ + regulator-suspend-microvolt = <3300000>; + regulator-on-in-suspend; + }; + + standby-ddr-off{ + regulator-suspend-microvolt = <3300000>; + regulator-on-in-suspend; + }; + }; + + v3v3:buck4{ + regulator-name = "v3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-over-current-protection; + regulator-initial-mode = <0>; + + lp-stop{ + regulator-suspend-microvolt = <3300000>; + regulator-on-in-suspend; + }; + + standby-ddr-sr{ + regulator-off-in-suspend; + }; + + standby-ddr-off{ + regulator-off-in-suspend; + }; + }; + + v1v8_audio:ldo1{ + regulator-name = "v1v8_audio"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + + standby-ddr-sr{ + regulator-off-in-suspend; + }; + + standby-ddr-off{ + regulator-off-in-suspend; + }; + }; + + v3v3_hdmi:ldo2{ + regulator-name = "v3v3_hdmi"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + + standby-ddr-sr{ + regulator-off-in-suspend; + }; + + standby-ddr-off{ + regulator-off-in-suspend; + }; + }; + + vtt_ddr:ldo3{ + regulator-name = "vtt_ddr"; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <750000>; + regulator-always-on; + regulator-over-current-protection; + + lp-stop{ + regulator-off-in-suspend; + }; + + standby-ddr-sr{ + regulator-off-in-suspend; + }; + + standby-ddr-off{ + regulator-off-in-suspend; + }; + }; + + vdd_usb:ldo4{ + regulator-name = "vdd_usb"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + + standby-ddr-sr{ + regulator-on-in-suspend; + }; + + standby-ddr-off{ + regulator-off-in-suspend; + }; + }; + + vdda:ldo5{ + regulator-name = "vdda"; + regulator-min-microvolt = <2900000>; + regulator-max-microvolt = <2900000>; + regulator-boot-on; + + standby-ddr-sr{ + regulator-off-in-suspend; + }; + + standby-ddr-off{ + regulator-off-in-suspend; + }; + }; + + v1v2_hdmi:ldo6{ + regulator-name = "v1v2_hdmi"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + + standby-ddr-sr{ + regulator-off-in-suspend; + }; + + standby-ddr-off{ + regulator-off-in-suspend; + }; + }; + + vref_ddr:vref_ddr{ + regulator-name = "vref_ddr"; + regulator-always-on; + regulator-over-current-protection; + + lp-stop{ + regulator-on-in-suspend; + }; + + standby-ddr-sr{ + regulator-on-in-suspend; + }; + + standby-ddr-off{ + regulator-off-in-suspend; + }; + }; + + bst_out:boost{ + regulator-name = "bst_out"; + }; + + vbus_otg:pwr_sw1{ + regulator-name = "vbus_otg"; + }; + + vbus_sw:pwr_sw2{ + regulator-name = "vbus_sw"; + regulator-active-discharge = <1>; + }; + }; + }; + /* USER CODE END i2c4 */ +}; + +&iwdg2{ + status = "okay"; + secure-status = "okay"; + + /* USER CODE BEGIN iwdg2 */ + timeout-sec = <32>; + /* USER CODE END iwdg2 */ +}; + +&pwr_regulators{ + status = "okay"; + secure-status = "okay"; + + /* USER CODE BEGIN pwr_regulators */ + system_suspend_supported_soc_modes = < + STM32_PM_CSLEEP_RUN + STM32_PM_CSTOP_ALLOW_LP_STOP + STM32_PM_CSTOP_ALLOW_STANDBY_DDR_SR + >; + system_off_soc_mode = ; + vdd-supply = <&vdd>; + vdd_3v3_usbfs-supply = <&vdd_usb>; + /* USER CODE END pwr_regulators */ +}; + +&rcc{ + status = "okay"; + secure-status = "okay"; + + /* USER CODE BEGIN rcc */ + /* USER CODE END rcc */ +}; + +&rng1{ + status = "okay"; + secure-status = "okay"; + + /* USER CODE BEGIN rng1 */ + /* USER CODE END rng1 */ +}; + +&rtc{ + pinctrl-names = "default"; + pinctrl-0 = <&rtc_pins_mx>; + status = "okay"; + secure-status = "okay"; + + /* USER CODE BEGIN rtc */ + /* USER CODE END rtc */ +}; + +&sdmmc1{ + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc1_pins_mx>; + status = "okay"; + + /* USER CODE BEGIN sdmmc1 */ + disable-wp; + st,neg-edge; + bus-width = <4>; + vmmc-supply = <&v3v3>; + /* USER CODE END sdmmc1 */ +}; + +&tamp{ + status = "okay"; + secure-status = "okay"; + + /* USER CODE BEGIN tamp */ + /* USER CODE END tamp */ +}; + +&uart4{ + pinctrl-names = "default"; + pinctrl-0 = <&uart4_pins_mx>; + status = "okay"; + + /* USER CODE BEGIN uart4 */ + /* USER CODE END uart4 */ +}; + +&usbotg_hs{ + status = "okay"; + + /* USER CODE BEGIN usbotg_hs */ + phys = <&usbphyc_port1 0>; + phy-names = "usb2-phy"; + usb-role-switch; + /* USER CODE END usbotg_hs */ +}; + +&usbphyc{ + status = "okay"; + + /* USER CODE BEGIN usbphyc */ + /* USER CODE END usbphyc */ +}; + +&usbphyc_port0{ + status = "okay"; + + /* USER CODE BEGIN usbphyc_port0 */ + phy-supply = <&vdd_usb>; + /* USER CODE END usbphyc_port0 */ +}; + +&usbphyc_port1{ + status = "okay"; + + /* USER CODE BEGIN usbphyc_port1 */ + phy-supply = <&vdd_usb>; + /* USER CODE END usbphyc_port1 */ +}; + +/* USER CODE BEGIN addons */ + +&cpu0{ + cpu-supply = <&vddcore>; +}; + +&cpu1{ + cpu-supply = <&vddcore>; +}; + +&nvmem_layout{ + nvmem-cells = <&cfg0_otp>, + <&part_number_otp>, + <&monotonic_otp>, + <&nand_otp>, + <&uid_otp>, + <&package_otp>, + <&hw2_otp>, + <&pkh_otp>, + <&board_id>; + nvmem-cell-names = "cfg0_otp", + "part_number_otp", + "monotonic_otp", + "nand_otp", + "uid_otp", + "package_otp", + "hw2_otp", + "pkh_otp", + "board_id"; +}; + +&timers15{ + secure-status = "okay"; + st,hsi-cal-input = <7>; + st,csi-cal-input = <8>; +}; + + +/* eMMC */ +&sdmmc2 { + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc2_pins_mx>; + non-removable; + no-sd; + no-sdio; + st,neg-edge; + bus-width = <4>; //bus-width 4 사용이면 4로 변경 + vmmc-supply = <&v3v3>; + vqmmc-supply = <&vdd>; + mmc-ddr-3_3v; + status = "okay"; +}; +/* USER CODE END addons */ + diff --git a/meta-st/meta-st-stm32mpu-hce/mx/STM32MP157C-DK2/DeviceTree/hce/u-boot/stm32mp15-mx.dtsi b/meta-st/meta-st-stm32mpu-hce/mx/STM32MP157C-DK2/DeviceTree/hce/u-boot/stm32mp15-mx.dtsi new file mode 100755 index 0000000..e1de4de --- /dev/null +++ b/meta-st/meta-st-stm32mpu-hce/mx/STM32MP157C-DK2/DeviceTree/hce/u-boot/stm32mp15-mx.dtsi @@ -0,0 +1,229 @@ +/* + * Copyright (C) 2015-2018, STMicroelectronics - All Rights Reserved + * + * SPDX-License-Identifier: GPL-2.0+ BSD-3-Clause + * + */ + + #ifdef DDR_N_1GB + +/* + * File generated by STMicroelectronics STM32CubeMX DDR Tool for MPUs + * DDR type: DDR3 / DDR3L + * DDR width: 16bits + * DDR density: 4Gb + * System frequency: 533000Khz + * Relaxed Timing Mode: false + * Address mapping type: RBC + * + * Save Date: 2020.06.30, save Time: 17:39:59 + */ + +#define DDR_MEM_NAME "DDR3-DDR3L 16bits 533000Khz" +#define DDR_MEM_SPEED 533000 +#define DDR_MEM_SIZE 0x20000000 + +#define DDR_MSTR 0x00041401 +#define DDR_MRCTRL0 0x00000010 +#define DDR_MRCTRL1 0x00000000 +#define DDR_DERATEEN 0x00000000 +#define DDR_DERATEINT 0x00800000 +#define DDR_PWRCTL 0x00000000 +#define DDR_PWRTMG 0x00400010 +#define DDR_HWLPCTL 0x00000000 +#define DDR_RFSHCTL0 0x00210000 +#define DDR_RFSHCTL3 0x00000000 +#define DDR_RFSHTMG 0x0081008B +#define DDR_CRCPARCTL0 0x00000000 +#define DDR_DRAMTMG0 0x121B2414 +#define DDR_DRAMTMG1 0x000A041C +#define DDR_DRAMTMG2 0x0608090F +#define DDR_DRAMTMG3 0x0050400C +#define DDR_DRAMTMG4 0x08040608 +#define DDR_DRAMTMG5 0x06060403 +#define DDR_DRAMTMG6 0x02020002 +#define DDR_DRAMTMG7 0x00000202 +#define DDR_DRAMTMG8 0x00001005 +#define DDR_DRAMTMG14 0x000000A0 +#define DDR_ZQCTL0 0xC2000040 +#define DDR_DFITMG0 0x02060105 +#define DDR_DFITMG1 0x00000202 +#define DDR_DFILPCFG0 0x07000000 +#define DDR_DFIUPD0 0xC0400003 +#define DDR_DFIUPD1 0x00000000 +#define DDR_DFIUPD2 0x00000000 +#define DDR_DFIPHYMSTR 0x00000000 +#define DDR_ODTCFG 0x06000600 +#define DDR_ODTMAP 0x00000001 +#define DDR_SCHED 0x00000C01 +#define DDR_SCHED1 0x00000000 +#define DDR_PERFHPR1 0x01000001 +#define DDR_PERFLPR1 0x08000200 +#define DDR_PERFWR1 0x08000400 +#define DDR_DBG0 0x00000000 +#define DDR_DBG1 0x00000000 +#define DDR_DBGCMD 0x00000000 +#define DDR_POISONCFG 0x00000000 +#define DDR_PCCFG 0x00000010 +#define DDR_PCFGR_0 0x00010000 +#define DDR_PCFGW_0 0x00000000 +#define DDR_PCFGQOS0_0 0x02100C03 +#define DDR_PCFGQOS1_0 0x00800100 +#define DDR_PCFGWQOS0_0 0x01100C03 +#define DDR_PCFGWQOS1_0 0x01000200 +#define DDR_PCFGR_1 0x00010000 +#define DDR_PCFGW_1 0x00000000 +#define DDR_PCFGQOS0_1 0x02100C03 +#define DDR_PCFGQOS1_1 0x00800040 +#define DDR_PCFGWQOS0_1 0x01100C03 +#define DDR_PCFGWQOS1_1 0x01000200 +#define DDR_ADDRMAP1 0x00070707 +#define DDR_ADDRMAP2 0x00000000 +#define DDR_ADDRMAP3 0x1F000000 +#define DDR_ADDRMAP4 0x00001F1F +#define DDR_ADDRMAP5 0x06060606 +#define DDR_ADDRMAP6 0x0F060606 +#define DDR_ADDRMAP9 0x00000000 +#define DDR_ADDRMAP10 0x00000000 +#define DDR_ADDRMAP11 0x00000000 +#define DDR_PGCR 0x01442E02 +#define DDR_PTR0 0x0022AA5B +#define DDR_PTR1 0x04841104 +#define DDR_PTR2 0x042DA068 +#define DDR_ACIOCR 0x10400812 +#define DDR_DXCCR 0x00000C40 +#define DDR_DSGCR 0xF200011F +#define DDR_DCR 0x0000000B +#define DDR_DTPR0 0x38D488D0 +#define DDR_DTPR1 0x098B00D8 +#define DDR_DTPR2 0x10023600 +#define DDR_MR0 0x00000840 +#define DDR_MR1 0x00000000 +#define DDR_MR2 0x00000208 +#define DDR_MR3 0x00000000 +#define DDR_ODTCR 0x00010000 +#define DDR_ZQ0CR1 0x00000038 +#define DDR_DX0GCR 0x0000CE81 +#define DDR_DX0DLLCR 0x40000000 +#define DDR_DX0DQTR 0xFFFFFFFF +#define DDR_DX0DQSTR 0x3DB02000 +#define DDR_DX1GCR 0x0000CE81 +#define DDR_DX1DLLCR 0x40000000 +#define DDR_DX1DQTR 0xFFFFFFFF +#define DDR_DX1DQSTR 0x3DB02000 +#define DDR_DX2GCR 0x0000CE80 +#define DDR_DX2DLLCR 0x40000000 +#define DDR_DX2DQTR 0xFFFFFFFF +#define DDR_DX2DQSTR 0x3DB02000 +#define DDR_DX3GCR 0x0000CE80 +#define DDR_DX3DLLCR 0x40000000 +#define DDR_DX3DQTR 0xFFFFFFFF +#define DDR_DX3DQSTR 0x3DB02000 + + +#else + + + +#define DDR_MEM_NAME "DDR3-DDR3L 16bits 533000Khz" +#define DDR_MEM_SPEED 533000 +#define DDR_MEM_SIZE 0x40000000 + +#define DDR_MSTR 0x00041401 +#define DDR_MRCTRL0 0x00000010 +#define DDR_MRCTRL1 0x00000000 +#define DDR_DERATEEN 0x00000000 +#define DDR_DERATEINT 0x00800000 +#define DDR_PWRCTL 0x00000000 +#define DDR_PWRTMG 0x00400010 +#define DDR_HWLPCTL 0x00000000 +#define DDR_RFSHCTL0 0x00210000 +#define DDR_RFSHCTL3 0x00000000 +#define DDR_RFSHTMG 0x0081008B +#define DDR_CRCPARCTL0 0x00000000 +#define DDR_DRAMTMG0 0x121B2414 +#define DDR_DRAMTMG1 0x000A041C +#define DDR_DRAMTMG2 0x0608090F +#define DDR_DRAMTMG3 0x0050400C +#define DDR_DRAMTMG4 0x08040608 +#define DDR_DRAMTMG5 0x06060403 +#define DDR_DRAMTMG6 0x02020002 +#define DDR_DRAMTMG7 0x00000202 +#define DDR_DRAMTMG8 0x00001005 +#define DDR_DRAMTMG14 0x000000A0 +#define DDR_ZQCTL0 0xC2000040 +#define DDR_DFITMG0 0x02060105 +#define DDR_DFITMG1 0x00000202 +#define DDR_DFILPCFG0 0x07000000 +#define DDR_DFIUPD0 0xC0400003 +#define DDR_DFIUPD1 0x00000000 +#define DDR_DFIUPD2 0x00000000 +#define DDR_DFIPHYMSTR 0x00000000 +#define DDR_ODTCFG 0x06000600 +#define DDR_ODTMAP 0x00000001 +#define DDR_SCHED 0x00000C01 +#define DDR_SCHED1 0x00000000 +#define DDR_PERFHPR1 0x01000001 +#define DDR_PERFLPR1 0x08000200 +#define DDR_PERFWR1 0x08000400 +#define DDR_DBG0 0x00000000 +#define DDR_DBG1 0x00000000 +#define DDR_DBGCMD 0x00000000 +#define DDR_POISONCFG 0x00000000 +#define DDR_PCCFG 0x00000010 +#define DDR_PCFGR_0 0x00010000 +#define DDR_PCFGW_0 0x00000000 +#define DDR_PCFGQOS0_0 0x02100C03 +#define DDR_PCFGQOS1_0 0x00800100 +#define DDR_PCFGWQOS0_0 0x01100C03 +#define DDR_PCFGWQOS1_0 0x01000200 +#define DDR_PCFGR_1 0x00010000 +#define DDR_PCFGW_1 0x00000000 +#define DDR_PCFGQOS0_1 0x02100C03 +#define DDR_PCFGQOS1_1 0x00800040 +#define DDR_PCFGWQOS0_1 0x01100C03 +#define DDR_PCFGWQOS1_1 0x01000200 +#define DDR_ADDRMAP1 0x00070707 +#define DDR_ADDRMAP2 0x00000000 +#define DDR_ADDRMAP3 0x1F000000 +#define DDR_ADDRMAP4 0x00001F1F +#define DDR_ADDRMAP5 0x06060606 +#define DDR_ADDRMAP6 0x06060606 +#define DDR_ADDRMAP9 0x00000000 +#define DDR_ADDRMAP10 0x00000000 +#define DDR_ADDRMAP11 0x00000000 +#define DDR_PGCR 0x01442E02 +#define DDR_PTR0 0x0022AA5B +#define DDR_PTR1 0x04841104 +#define DDR_PTR2 0x042DA068 +#define DDR_ACIOCR 0x10400812 +#define DDR_DXCCR 0x00000C40 +#define DDR_DSGCR 0xF200011F +#define DDR_DCR 0x0000000B +#define DDR_DTPR0 0x38D488D0 +#define DDR_DTPR1 0x098B00D8 +#define DDR_DTPR2 0x10023600 +#define DDR_MR0 0x00000840 +#define DDR_MR1 0x00000000 +#define DDR_MR2 0x00000208 +#define DDR_MR3 0x00000000 +#define DDR_ODTCR 0x00010000 +#define DDR_ZQ0CR1 0x00000038 +#define DDR_DX0GCR 0x0000CE81 +#define DDR_DX0DLLCR 0x40000000 +#define DDR_DX0DQTR 0x33333333 +#define DDR_DX0DQSTR 0x3DB02000 +#define DDR_DX1GCR 0x0000CE81 +#define DDR_DX1DLLCR 0x40000000 +#define DDR_DX1DQTR 0x33333333 +#define DDR_DX1DQSTR 0x3DB02000 +#define DDR_DX2GCR 0x0000CE80 +#define DDR_DX2DLLCR 0x40000000 +#define DDR_DX2DQTR 0xFFFFFFFF +#define DDR_DX2DQSTR 0x3DB02000 +#define DDR_DX3GCR 0x0000CE80 +#define DDR_DX3DLLCR 0x40000000 +#define DDR_DX3DQTR 0xFFFFFFFF +#define DDR_DX3DQSTR 0x3DB02000 + +#endif \ No newline at end of file diff --git a/meta-st/meta-st-stm32mpu-hce/mx/STM32MP157C-DK2/DeviceTree/hce/u-boot/stm32mp157c-hce-mx-u-boot.dtsi b/meta-st/meta-st-stm32mpu-hce/mx/STM32MP157C-DK2/DeviceTree/hce/u-boot/stm32mp157c-hce-mx-u-boot.dtsi new file mode 100644 index 0000000..cba8efa --- /dev/null +++ b/meta-st/meta-st-stm32mpu-hce/mx/STM32MP157C-DK2/DeviceTree/hce/u-boot/stm32mp157c-hce-mx-u-boot.dtsi @@ -0,0 +1,287 @@ +/* SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause*/ +/* + * Copyright (C) 2020, STMicroelectronics - All Rights Reserved + * Author: STM32CubeMX code generation for STMicroelectronics. + */ + +/* For more information on Device Tree configuration, please refer to + * https://wiki.st.com/stm32mpu/wiki/Category:Device_tree_configuration + */ + +#include +#include "stm32mp15-mx.dtsi" + + +#include "stm32mp15-u-boot.dtsi" +#include "stm32mp15-ddr.dtsi" + +/* USER CODE BEGIN includes */ +/* USER CODE END includes */ + +/ { + + /* USER CODE BEGIN root */ + + aliases{ + i2c3 = &i2c4; + /* by SDT */ + /* by mirika */ + mmc0 = &sdmmc1; + mmc1 = &sdmmc2; + mmc2 = &sdmmc3; + usb0 = &usbotg_hs; + }; + + config{ + u-boot,boot-led = "heartbeat"; + u-boot,error-led = "error"; + u-boot,mmc-env-partition = "ssbl"; + st,adc_usb_pd = <&adc1 18>, <&adc1 19>; + st,fastboot-gpios = <&gpioa 13 GPIO_ACTIVE_LOW>; + st,stm32prog-gpios = <&gpioa 14 GPIO_ACTIVE_LOW>; + }; + + led{ + + red{ + label = "error"; + gpios = <&gpioa 13 GPIO_ACTIVE_LOW>; + default-state = "off"; + status = "okay"; + }; + }; + /* USER CODE END root */ + + clocks { + u-boot,dm-pre-reloc; + + /* USER CODE BEGIN clocks */ + /* USER CODE END clocks */ + +#ifndef CONFIG_STM32MP1_TRUSTED + clk_lsi: clk-lsi { + u-boot,dm-pre-reloc; + + /* USER CODE BEGIN clk_lsi */ + /* USER CODE END clk_lsi */ + }; + clk_hsi: clk-hsi { + u-boot,dm-pre-reloc; + + /* USER CODE BEGIN clk_hsi */ + /* USER CODE END clk_hsi */ + }; + clk_csi: clk-csi { + u-boot,dm-pre-reloc; + status = "disabled"; + + /* USER CODE BEGIN clk_csi */ + /* USER CODE END clk_csi */ + }; + clk_lse: clk-lse { + u-boot,dm-pre-reloc; + st,drive = < LSEDRV_MEDIUM_HIGH >; + + /* USER CODE BEGIN clk_lse */ + /* USER CODE END clk_lse */ + }; + clk_hse: clk-hse { + u-boot,dm-pre-reloc; + st,digbypass; + + /* USER CODE BEGIN clk_hse */ + /* USER CODE END clk_hse */ + }; +#endif /*CONFIG_STM32MP1_TRUSTED*/ + }; + +}; /*root*/ + +#ifndef CONFIG_STM32MP1_TRUSTED + +&rcc { + u-boot,dm-pre-reloc; + st,clksrc = < + CLK_MPU_PLL1P + CLK_AXI_PLL2P + CLK_MCU_PLL3P + CLK_PLL12_HSE + CLK_PLL3_HSE + CLK_PLL4_HSE + CLK_RTC_LSE + CLK_MCO1_DISABLED + CLK_MCO2_DISABLED + >; + st,clkdiv = < + 1 /*MPU*/ + 0 /*AXI*/ + 0 /*MCU*/ + 1 /*APB1*/ + 1 /*APB2*/ + 1 /*APB3*/ + 1 /*APB4*/ + 2 /*APB5*/ + 23 /*RTC*/ + 0 /*MCO1*/ + 0 /*MCO2*/ + >; + st,pkcs = < + CLK_CKPER_HSE + CLK_ETH_DISABLED + CLK_SDMMC12_PLL4P + CLK_DSI_DSIPLL + CLK_STGEN_HSE + CLK_USBPHY_HSE + CLK_SPI2S1_DISABLED + CLK_SPI2S23_PLL3Q + CLK_SPI45_PCLK2 + CLK_SPI6_DISABLED + CLK_I2C46_HSI + CLK_SDMMC3_DISABLED + CLK_USBO_USBPHY + CLK_ADC_CKPER + CLK_CEC_LSE + CLK_I2C12_HSI + CLK_I2C35_DISABLED + CLK_UART1_DISABLED + CLK_UART24_HSI + CLK_UART35_DISABLED + CLK_UART6_DISABLED + CLK_UART78_DISABLED + CLK_SPDIF_DISABLED + CLK_SAI1_DISABLED + CLK_SAI2_DISABLED + CLK_SAI3_DISABLED + CLK_SAI4_DISABLED + CLK_RNG1_LSI + CLK_LPTIM1_DISABLED + CLK_LPTIM23_DISABLED + CLK_LPTIM45_DISABLED + >; + + #if 0 + /* Added by SDT */ + /* pll 411Mhz */ + pll1:st,pll@0 { + cfg = < 1 33 0 1 1 PQR(1,0,0) >; + frac = < 0x800 >; + u-boot,dm-pre-reloc; + }; + /* */ + #endif + + pll2:st,pll@1 { + compatible = "st,stm32mp1-pll"; + reg = <1>; + cfg = < 2 65 1 0 0 PQR(1,1,1) >; + frac = < 0x1400 >; + u-boot,dm-pre-reloc; + }; + pll3:st,pll@2 { + compatible = "st,stm32mp1-pll"; + reg = <2>; + cfg = < 1 33 1 16 36 PQR(1,1,0) >; + frac = < 0x1a04 >; + u-boot,dm-pre-reloc; + }; + pll4:st,pll@3 { + compatible = "st,stm32mp1-pll"; + reg = <3>; + cfg = < 3 98 5 7 7 PQR(1,1,0) >; + u-boot,dm-pre-reloc; + }; +}; + +&i2c4{ + u-boot,dm-pre-reloc; + + /* USER CODE BEGIN i2c4 */ + /* USER CODE END i2c4 */ +}; + +&sdmmc1{ + u-boot,dm-pre-reloc; + + /* USER CODE BEGIN sdmmc1 */ + /* USER CODE END sdmmc1 */ +}; + +#endif /*CONFIG_STM32MP1_TRUSTED*/ + +&cryp1{ + u-boot,dm-pre-reloc; + + /* USER CODE BEGIN cryp1 */ + /* USER CODE END cryp1 */ +}; + +&hash1{ + u-boot,dm-pre-reloc; + + /* USER CODE BEGIN hash1 */ + /* USER CODE END hash1 */ +}; + +&uart4{ + u-boot,dm-pre-reloc; + + /* USER CODE BEGIN uart4 */ + /* USER CODE END uart4 */ +}; + +&usbotg_hs{ + u-boot,dm-pre-reloc; + + /* USER CODE BEGIN usbotg_hs */ + u-boot,force-b-session-valid; + hnp-srp-disable; + dr_mode = "peripheral"; + /* USER CODE END usbotg_hs */ +}; + +&usbphyc{ + u-boot,dm-pre-reloc; + + /* USER CODE BEGIN usbphyc */ + /* USER CODE END usbphyc */ +}; + +&usbphyc_port0{ + u-boot,dm-pre-reloc; + + /* USER CODE BEGIN usbphyc_port0 */ + /* USER CODE END usbphyc_port0 */ +}; + +&usbphyc_port1{ + u-boot,dm-pre-reloc; + + /* USER CODE BEGIN usbphyc_port1 */ + /* USER CODE END usbphyc_port1 */ +}; + +/* USER CODE BEGIN addons */ + +&adc{ + status = "okay"; +}; + +#ifndef CONFIG_STM32MP1_TRUSTED +&i2s2{ + clocks = <&rcc SPI2>, <&rcc SPI2_K>, <&rcc PLL3_Q>, <&rcc PLL3_R>; +}; + +&pmic{ + u-boot,dm-pre-reloc; +}; + +&sai2{ + clocks = <&rcc SAI2>, <&rcc PLL3_Q>, <&rcc PLL3_R>; +}; +#endif /*CONFIG_STM32MP1_TRUSTED*/ + + + + +/* USER CODE END addons */ + diff --git a/meta-st/meta-st-stm32mpu-hce/mx/STM32MP157C-DK2/DeviceTree/hce/u-boot/stm32mp157c-hce-mx.dts b/meta-st/meta-st-stm32mpu-hce/mx/STM32MP157C-DK2/DeviceTree/hce/u-boot/stm32mp157c-hce-mx.dts new file mode 100644 index 0000000..865431c --- /dev/null +++ b/meta-st/meta-st-stm32mpu-hce/mx/STM32MP157C-DK2/DeviceTree/hce/u-boot/stm32mp157c-hce-mx.dts @@ -0,0 +1,1444 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */ +/* + * Copyright (C) STMicroelectronics 2020 - All Rights Reserved + * Author: STM32CubeMX code generation for STMicroelectronics. + */ + +/* For more information on Device Tree configuration, please refer to + * https://wiki.st.com/stm32mpu/wiki/Category:Device_tree_configuration + */ + +/dts-v1/; +#include + +#include "stm32mp157.dtsi" +#include "stm32mp15xc.dtsi" +#include "stm32mp15xxac-pinctrl.dtsi" +#include "stm32mp157-m4-srm.dtsi" + +/* USER CODE BEGIN includes */ +#include +#include +/* USER CODE END includes */ + +/ { + model = "STMicroelectronics STM32MP157C-DK2 STM32CubeMX board"; + compatible = "st,stm32mp157c-hce-mx", "st,stm32mp157"; + + memory@c0000000 { + device_type = "memory"; + reg = <0xc0000000 0x20000000>; + + /* USER CODE BEGIN memory */ + /* USER CODE END memory */ + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + /* USER CODE BEGIN reserved-memory */ + + mcuram2:mcuram2@10000000{ + compatible = "shared-dma-pool"; + reg = <0x10000000 0x40000>; + no-map; + }; + + vdev0vring0:vdev0vring0@10040000{ + compatible = "shared-dma-pool"; + reg = <0x10040000 0x1000>; + no-map; + }; + + vdev0vring1:vdev0vring1@10041000{ + compatible = "shared-dma-pool"; + reg = <0x10041000 0x1000>; + no-map; + }; + + vdev0buffer:vdev0buffer@10042000{ + compatible = "shared-dma-pool"; + reg = <0x10042000 0x4000>; + no-map; + }; + + mcuram:mcuram@30000000{ + compatible = "shared-dma-pool"; + reg = <0x30000000 0x40000>; + no-map; + }; + + retram:retram@38000000{ + compatible = "shared-dma-pool"; + reg = <0x38000000 0x10000>; + no-map; + }; + + gpu_reserved:gpu@da000000{ + reg = <0xda000000 0x4000000>; + no-map; + }; + + optee_memory:optee@0xde000000{ + reg = <0xde000000 0x02000000>; + no-map; + status = "okay"; + }; + /* USER CODE END reserved-memory */ + }; + + /* USER CODE BEGIN root */ + + led{ + compatible = "gpio-leds"; + + blue{ + label = "heartbeat"; + gpios = <&gpiod 11 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + default-state = "off"; + }; + }; + + sound{ + compatible = "audio-graph-card"; + label = "STM32MP1-DK"; + routing = "Playback", "MCLK", + "Capture", "MCLK", + "MICL", "Mic Bias"; + dais = <&sai2a_port &sai2b_port &i2s2_port>; + status = "okay"; + }; + + usb_phy_tuning:usb-phy-tuning{ + st,hs-dc-level = <2>; + st,fs-rftime-tuning; + st,hs-rftime-reduction; + st,hs-current-trim = <15>; + st,hs-impedance-trim = <1>; + st,squelch-level = <3>; + st,hs-rx-offset = <2>; + st,no-lsfs-sc; + }; + + vin:vin{ + compatible = "regulator-fixed"; + regulator-name = "vin"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + }; + + aliases{ + ethernet0 = ðernet0; + serial0 = &uart4; + serial1 = &usart3; + serial2 = &uart7; + serial3 = &usart2; + }; + + chosen{ + stdout-path = "serial0:115200n8"; + }; + + wifi_pwrseq:wifi-pwrseq{ + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&gpioh 4 GPIO_ACTIVE_LOW>; + }; + /* USER CODE END root */ + + clocks { + + /* USER CODE BEGIN clocks */ + /* USER CODE END clocks */ + +#ifndef CONFIG_STM32MP1_TRUSTED + clk_lsi: clk-lsi { + clock-frequency = <32000>; + }; + clk_hsi: clk-hsi { + clock-frequency = <64000000>; + }; + clk_csi: clk-csi { + clock-frequency = <4000000>; + }; + clk_lse: clk-lse { + clock-frequency = <32768>; + }; + clk_hse: clk-hse { + clock-frequency = <24000000>; + }; +#endif /*CONFIG_STM32MP1_TRUSTED*/ + }; + +}; /*root*/ + +&pinctrl { + u-boot,dm-pre-reloc; + + adc_pins_mx: adc_mx-0 { + pins { + pinmux = , /* ADC1_INP18 */ + ; /* ADC1_INP19 */ + }; + }; + + adc_sleep_pins_mx: adc_sleep_mx-0 { + pins { + pinmux = , /* ADC1_INP18 */ + ; /* ADC1_INP19 */ + }; + }; + + eth1_pins_mx: eth1_mx-0 { + pins1 { + pinmux = , /* ETH1_RX_CLK */ + , /* ETH1_RX_CTL */ + , /* ETH1_RXD2 */ + , /* ETH1_RXD3 */ + , /* ETH1_RXD0 */ + ; /* ETH1_RXD1 */ + bias-disable; + }; + pins2 { + pinmux = ; /* ETH1_MDIO */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins3 { + pinmux = , /* ETH1_TX_CTL */ + , /* ETH1_MDC */ + , /* ETH1_TXD2 */ + , /* ETH1_TXD3 */ + , /* ETH1_GTX_CLK */ + , /* ETH1_CLK125 */ + , /* ETH1_TXD0 */ + ; /* ETH1_TXD1 */ + bias-disable; + drive-push-pull; + slew-rate = <2>; + }; + }; + + eth1_sleep_pins_mx: eth1_sleep_mx-0 { + pins { + pinmux = , /* ETH1_RX_CLK */ + , /* ETH1_MDIO */ + , /* ETH1_RX_CTL */ + , /* ETH1_RXD2 */ + , /* ETH1_RXD3 */ + , /* ETH1_TX_CTL */ + , /* ETH1_MDC */ + , /* ETH1_TXD2 */ + , /* ETH1_RXD0 */ + , /* ETH1_RXD1 */ + , /* ETH1_TXD3 */ + , /* ETH1_GTX_CLK */ + , /* ETH1_CLK125 */ + , /* ETH1_TXD0 */ + ; /* ETH1_TXD1 */ + }; + }; + + hdmi_cec_pins_mx: hdmi_cec_mx-0 { + pins { + pinmux = ; /* CEC */ + bias-disable; + drive-open-drain; + slew-rate = <0>; + }; + }; + + hdmi_cec_sleep_pins_mx: hdmi_cec_sleep_mx-0 { + pins { + pinmux = ; /* CEC */ + }; + }; + + i2c1_pins_mx: i2c1_mx-0 { + pins { + pinmux = , /* I2C1_SCL */ + ; /* I2C1_SDA */ + bias-disable; + drive-open-drain; + slew-rate = <0>; + }; + }; + + i2c1_sleep_pins_mx: i2c1_sleep_mx-0 { + pins { + pinmux = , /* I2C1_SCL */ + ; /* I2C1_SDA */ + }; + }; + + i2s2_pins_mx: i2s2_mx-0 { + pins { + pinmux = , /* I2S2_CK */ + , /* I2S2_WS */ + ; /* I2S2_SDO */ + bias-disable; + drive-push-pull; + slew-rate = <1>; + }; + }; + + i2s2_sleep_pins_mx: i2s2_sleep_mx-0 { + pins { + pinmux = , /* I2S2_CK */ + , /* I2S2_WS */ + ; /* I2S2_SDO */ + }; + }; + + rtc_pins_mx: rtc_mx-0 { + pins { + pinmux = ; /* RTC_LSCO */ + }; + }; + + rtc_sleep_pins_mx: rtc_sleep_mx-0 { + pins { + pinmux = ; /* RTC_LSCO */ + }; + }; + + sai2a_pins_mx: sai2a_mx-0 { + pins { + pinmux = , /* SAI2_MCLK_A */ + , /* SAI2_SCK_A */ + , /* SAI2_SD_A */ + ; /* SAI2_FS_A */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + }; + + sai2a_sleep_pins_mx: sai2a_sleep_mx-0 { + pins { + pinmux = , /* SAI2_MCLK_A */ + , /* SAI2_SCK_A */ + , /* SAI2_SD_A */ + ; /* SAI2_FS_A */ + }; + }; + + sai2b_pins_mx: sai2b_mx-0 { + pins { + pinmux = ; /* SAI2_SD_B */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + }; + + sai2b_sleep_pins_mx: sai2b_sleep_mx-0 { + pins { + pinmux = ; /* SAI2_SD_B */ + }; + }; + + sdmmc1_pins_mx: sdmmc1_mx-0 { + u-boot,dm-pre-reloc; + pins1 { + u-boot,dm-pre-reloc; + pinmux = , /* SDMMC1_D0 */ + , /* SDMMC1_D1 */ + , /* SDMMC1_D2 */ + , /* SDMMC1_D3 */ + ; /* SDMMC1_CMD */ + bias-disable; + drive-push-pull; + slew-rate = <1>; + }; + pins2 { + u-boot,dm-pre-reloc; + pinmux = ; /* SDMMC1_CK */ + bias-disable; + drive-push-pull; + slew-rate = <2>; + }; + }; + + sdmmc1_opendrain_pins_mx: sdmmc1_opendrain_mx-0 { + u-boot,dm-pre-reloc; + pins1 { + u-boot,dm-pre-reloc; + pinmux = , /* SDMMC1_D0 */ + , /* SDMMC1_D1 */ + , /* SDMMC1_D2 */ + ; /* SDMMC1_D3 */ + bias-disable; + drive-push-pull; + slew-rate = <1>; + }; + pins2 { + u-boot,dm-pre-reloc; + pinmux = ; /* SDMMC1_CK */ + bias-disable; + drive-push-pull; + slew-rate = <2>; + }; + pins3 { + u-boot,dm-pre-reloc; + pinmux = ; /* SDMMC1_CMD */ + bias-disable; + drive-open-drain; + slew-rate = <1>; + }; + }; + + sdmmc1_sleep_pins_mx: sdmmc1_sleep_mx-0 { + u-boot,dm-pre-reloc; + pins { + u-boot,dm-pre-reloc; + pinmux = , /* SDMMC1_D0 */ + , /* SDMMC1_D1 */ + , /* SDMMC1_D2 */ + , /* SDMMC1_D3 */ + , /* SDMMC1_CK */ + ; /* SDMMC1_CMD */ + }; + }; + + sdmmc2_pins_mx: sdmmc2_mx-0 { + pins1 { + pinmux = , /* SDMMC2_D2 */ + , /* SDMMC2_D3 */ + , /* SDMMC2_D0 */ + , /* SDMMC2_D1 */ + ; /* SDMMC2_CMD */ + bias-disable; + drive-push-pull; + slew-rate = <1>; + }; + pins2 { + pinmux = ; /* SDMMC2_CK */ + bias-disable; + drive-push-pull; + slew-rate = <2>; + }; + }; + + sdmmc2_opendrain_pins_mx: sdmmc2_opendrain_mx-0 { + pins1 { + pinmux = , /* SDMMC2_D2 */ + , /* SDMMC2_D3 */ + , /* SDMMC2_D0 */ + ; /* SDMMC2_D1 */ + bias-disable; + drive-push-pull; + slew-rate = <1>; + }; + pins2 { + pinmux = ; /* SDMMC2_CK */ + bias-disable; + drive-push-pull; + slew-rate = <2>; + }; + pins3 { + pinmux = ; /* SDMMC2_CMD */ + bias-disable; + drive-open-drain; + slew-rate = <1>; + }; + }; + + sdmmc2_sleep_pins_mx: sdmmc2_sleep_mx-0 { + pins { + pinmux = , /* SDMMC2_D2 */ + , /* SDMMC2_D3 */ + , /* SDMMC2_D0 */ + , /* SDMMC2_D1 */ + , /* SDMMC2_CK */ + ; /* SDMMC2_CMD */ + }; + }; + + + + spi5_pins_mx: spi5_mx-0 { + pins { + pinmux = , /* SPI5_MISO */ + , /* SPI5_MOSI */ + ; /* SPI5_SCK */ + bias-disable; + drive-push-pull; + slew-rate = <1>; + }; + }; + + spi5_sleep_pins_mx: spi5_sleep_mx-0 { + pins { + pinmux = , /* SPI5_MISO */ + , /* SPI5_MOSI */ + ; /* SPI5_SCK */ + }; + }; + + uart4_pins_mx: uart4_mx-0 { + u-boot,dm-pre-reloc; + pins1 { + u-boot,dm-pre-reloc; + pinmux = ; /* UART4_RX */ + bias-pull-up; + }; + pins2 { + u-boot,dm-pre-reloc; + pinmux = ; /* UART4_TX */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + }; + + uart4_sleep_pins_mx: uart4_sleep_mx-0 { + u-boot,dm-pre-reloc; + pins { + u-boot,dm-pre-reloc; + pinmux = , /* UART4_RX */ + ; /* UART4_TX */ + }; + }; + + usart2_pins_mx: usart2_mx-0 { + pins1 { + pinmux = , /* USART2_CTS */ + ; /* USART2_RX */ + bias-disable; + }; + pins2 { + pinmux = , /* USART2_RTS */ + ; /* USART2_TX */ + bias-disable; + drive-push-pull; + slew-rate = <3>; + }; + }; + + usart2_sleep_pins_mx: usart2_sleep_mx-0 { + pins { + pinmux = , /* USART2_CTS */ + , /* USART2_RTS */ + , /* USART2_TX */ + ; /* USART2_RX */ + }; + }; + + + + /* USER CODE BEGIN pinctrl */ + stusb1600_pins_a: stusb1600-0 { + pins { + pinmux = ; + bias-pull-up; + }; + }; + + #if 0 + /*Addrd by mirika@SDT */ + usart3_pins_mx: usart3_mx-0 { + pins1 { + pinmux = , /* USART3_TX */ + ; /* USART3_RTS */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins2 { + pinmux = , /* USART3_RX */ + ; /* USART3_CTS */ + bias-disable; + }; + }; + + usart3_sleep_pins_mx: usart3_sleep_mx-0 { + pins { + pinmux = , /* USART3_TX */ + , /* USART3_RX */ + , /* USART3_CTS */ + ; /* USART3_RTS */ + }; + }; + #endif + + + /* USER CODE END pinctrl */ +}; + +&pinctrl_z { + u-boot,dm-pre-reloc; + + i2c4_pins_z_mx: i2c4_mx-0 { + u-boot,dm-pre-reloc; + pins { + u-boot,dm-pre-reloc; + pinmux = , /* I2C4_SCL */ + ; /* I2C4_SDA */ + bias-disable; + drive-open-drain; + slew-rate = <0>; + }; + }; + + i2c4_sleep_pins_z_mx: i2c4_sleep_mx-0 { + u-boot,dm-pre-reloc; + pins { + u-boot,dm-pre-reloc; + pinmux = , /* I2C4_SCL */ + ; /* I2C4_SDA */ + }; + }; + + /* USER CODE BEGIN pinctrl_z */ + /* USER CODE END pinctrl_z */ +}; + +&m4_rproc{ + /*Restriction: "memory-region" property is not managed - please to use User-Section if needed*/ + mboxes = <&ipcc 0>, <&ipcc 1>, <&ipcc 2>; + mbox-names = "vq0", "vq1", "shutdown"; + status = "okay"; + + /* USER CODE BEGIN m4_rproc */ + memory-region = <&retram>, <&mcuram>, <&mcuram2>, <&vdev0vring0>, + <&vdev0vring1>, <&vdev0buffer>; + interrupt-parent = <&exti>; + interrupts = <68 1>; + wakeup-source; + /* USER CODE END m4_rproc */ +}; + +&adc{ + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&adc_pins_mx>; + pinctrl-1 = <&adc_sleep_pins_mx>; + status = "okay"; + + /* USER CODE BEGIN adc */ + vdd-supply = <&vdd>; + vdda-supply = <&vdd>; + vref-supply = <&vrefbuf>; + + adc1:adc@0{ + st,min-sample-time-nsecs = <5000>; + st,adc-channels = <0 1 6 13 18 19>; + status = "okay"; + }; + + adc2:adc@100{ + st,adc-channels = <0 1 2 6 18 19>; + st,min-sample-time-nsecs = <5000>; + status = "okay"; + }; + /* USER CODE END adc */ +}; + +&bsec{ + status = "okay"; + + /* USER CODE BEGIN bsec */ + /* USER CODE END bsec */ +}; + +&cec{ + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&hdmi_cec_pins_mx>; + pinctrl-1 = <&hdmi_cec_sleep_pins_mx>; + status = "okay"; + + /* USER CODE BEGIN cec */ + /* USER CODE END cec */ +}; + +&crc1{ + status = "okay"; + + /* USER CODE BEGIN crc1 */ + /* USER CODE END crc1 */ +}; + +&cryp1{ + u-boot,dm-pre-reloc; + status = "okay"; + + /* USER CODE BEGIN cryp1 */ + /* USER CODE END cryp1 */ +}; + +&dma1{ + status = "okay"; + + /* USER CODE BEGIN dma1 */ + sram = <&dma_pool>; + /* USER CODE END dma1 */ +}; + +&dma2{ + status = "okay"; + + /* USER CODE BEGIN dma2 */ + sram = <&dma_pool>; + /* USER CODE END dma2 */ +}; + +&dmamux1{ + + dma-masters = <&dma1 &dma2>; + dma-channels = <16>; + + status = "okay"; + + /* USER CODE BEGIN dmamux1 */ + /* USER CODE END dmamux1 */ +}; + +&dsi{ + status = "okay"; + + /* USER CODE BEGIN dsi */ + #address-cells = <1>; + #size-cells = <0>; + + ports{ + #address-cells = <1>; + #size-cells = <0>; + + port@0{ + reg = <0>; + + dsi_in:endpoint{ + remote-endpoint = <<dc_ep1_out>; + }; + }; + + port@1{ + reg = <1>; + + dsi_out:endpoint{ + remote-endpoint = <&panel_in>; + }; + }; + }; + + panel_otm8009a:panel-otm8009a@0{ + compatible = "orisetech,otm8009a"; + reg = <0>; + reset-gpios = <&gpioe 4 GPIO_ACTIVE_LOW>; + power-supply = <&v3v3>; + status = "okay"; + + port{ + + panel_in:endpoint{ + remote-endpoint = <&dsi_out>; + }; + }; + }; + /* USER CODE END dsi */ +}; + +&dts{ + status = "okay"; + + /* USER CODE BEGIN dts */ + /* USER CODE END dts */ +}; + +ðernet0{ + pinctrl-names = "default", "sleep"; + pinctrl-0 = <ð1_pins_mx>; + pinctrl-1 = <ð1_sleep_pins_mx>; + status = "okay"; + + /* USER CODE BEGIN ethernet0 */ + phy-mode = "rgmii-id"; + max-speed = <1000>; + phy-handle = <&phy0>; + + mdio0{ + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dwmac-mdio"; + + phy0:ethernet-phy@0{ + reg = <0>; + }; + }; + /* USER CODE END ethernet0 */ +}; + +&gpu{ + status = "okay"; + + /* USER CODE BEGIN gpu */ + contiguous-area = <&gpu_reserved>; + /* USER CODE END gpu */ +}; + +&hash1{ + u-boot,dm-pre-reloc; + status = "okay"; + + /* USER CODE BEGIN hash1 */ + /* USER CODE END hash1 */ +}; + +&hsem{ + status = "okay"; + + /* USER CODE BEGIN hsem */ + /* USER CODE END hsem */ +}; + +&i2c1{ + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&i2c1_pins_mx>; + pinctrl-1 = <&i2c1_sleep_pins_mx>; + status = "okay"; + + /* USER CODE BEGIN i2c1 */ + i2c-scl-rising-time-ns = <100>; + i2c-scl-falling-time-ns = <7>; + /delete-property/ dmas; + /delete-property/ dma-names; + + hdmi-transmitter@39{ + compatible = "sil,sii9022"; + reg = <0x39>; + iovcc-supply = <&v3v3_hdmi>; + cvcc12-supply = <&v1v2_hdmi>; + reset-gpios = <&gpioa 10 GPIO_ACTIVE_LOW>; + interrupts = <1 IRQ_TYPE_EDGE_FALLING>; + interrupt-parent = <&gpiog>; + #sound-dai-cells = <0>; + status = "okay"; + + ports{ + #address-cells = <1>; + #size-cells = <0>; + + port@0{ + reg = <0>; + + sii9022_in:endpoint{ + remote-endpoint = <<dc_ep0_out>; + }; + }; + + port@3{ + reg = <3>; + + sii9022_tx_endpoint:endpoint{ + remote-endpoint = <&i2s2_endpoint>; + }; + }; + }; + }; + + cs42l51:cs42l51@4a{ + compatible = "cirrus,cs42l51"; + reg = <0x4a>; + #sound-dai-cells = <0>; + VL-supply = <&v3v3>; + VD-supply = <&v1v8_audio>; + VA-supply = <&v1v8_audio>; + VAHP-supply = <&v1v8_audio>; + reset-gpios = <&gpiog 9 GPIO_ACTIVE_LOW>; + clocks = <&sai2a>; + clock-names = "MCLK"; + status = "okay"; + + cs42l51_port:port{ + #address-cells = <1>; + #size-cells = <0>; + + cs42l51_tx_endpoint:endpoint@0{ + reg = <0>; + remote-endpoint = <&sai2a_endpoint>; + frame-master; + bitclock-master; + }; + + cs42l51_rx_endpoint:endpoint@1{ + reg = <1>; + remote-endpoint = <&sai2b_endpoint>; + frame-master; + bitclock-master; + }; + }; + }; + + touchscreen@2a{ + compatible = "focaltech,ft6236"; + reg = <0x2a>; + interrupts = <2 2>; + interrupt-parent = <&gpiof>; + interrupt-controller; + touchscreen-size-x = <480>; + touchscreen-size-y = <800>; + panel = <&panel_otm8009a>; + status = "okay"; + }; + + touchscreen@38{ + compatible = "focaltech,ft6236"; + reg = <0x38>; + interrupts = <2 2>; + interrupt-parent = <&gpiof>; + interrupt-controller; + touchscreen-size-x = <480>; + touchscreen-size-y = <800>; + panel = <&panel_otm8009a>; + status = "okay"; + }; + /* USER CODE END i2c1 */ +}; + +&i2c4{ + u-boot,dm-pre-reloc; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&i2c4_pins_z_mx>; + pinctrl-1 = <&i2c4_sleep_pins_z_mx>; + status = "okay"; + + /* USER CODE BEGIN i2c4 */ + i2c-scl-rising-time-ns = <185>; + i2c-scl-falling-time-ns = <20>; + clock-frequency = <400000>; + /delete-property/ dmas; + /delete-property/ dma-names; + + stusb1600@28{ + compatible = "st,stusb1600"; + reg = <0x28>; + interrupts = <11 IRQ_TYPE_EDGE_FALLING>; + interrupt-parent = <&gpioi>; + pinctrl-names = "default"; + pinctrl-0 = <&stusb1600_pins_a>; + status = "okay"; + vdd-supply = <&vin>; + + connector{ + compatible = "usb-c-connector"; + label = "USB-C"; + power-role = "dual"; + power-opmode = "default"; + + port{ + + con_usbotg_hs_ep:endpoint{ + remote-endpoint = <&usbotg_hs_ep>; + }; + }; + }; + }; + + pmic:stpmic@33{ + compatible = "st,stpmic1"; + reg = <0x33>; + interrupts-extended = <&exti_pwr 55 IRQ_TYPE_EDGE_FALLING>; + interrupt-controller; + #interrupt-cells = <2>; + status = "okay"; + + regulators{ + compatible = "st,stpmic1-regulators"; + buck1-supply = <&vin>; + buck2-supply = <&vin>; + buck3-supply = <&vin>; + buck4-supply = <&vin>; + ldo1-supply = <&v3v3>; + ldo2-supply = <&vin>; + ldo3-supply = <&vdd_ddr>; + ldo4-supply = <&vin>; + ldo5-supply = <&vin>; + ldo6-supply = <&v3v3>; + vref_ddr-supply = <&vin>; + boost-supply = <&vin>; + pwr_sw1-supply = <&bst_out>; + pwr_sw2-supply = <&bst_out>; + + vddcore:buck1{ + regulator-name = "vddcore"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1350000>; + regulator-always-on; + regulator-initial-mode = <0>; + regulator-over-current-protection; + }; + + vdd_ddr:buck2{ + regulator-name = "vdd_ddr"; + regulator-min-microvolt = <1350000>; + regulator-max-microvolt = <1350000>; + regulator-always-on; + regulator-initial-mode = <0>; + regulator-over-current-protection; + }; + + vdd:buck3{ + regulator-name = "vdd"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + st,mask-reset; + regulator-initial-mode = <0>; + regulator-over-current-protection; + }; + + v3v3:buck4{ + regulator-name = "v3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-over-current-protection; + regulator-initial-mode = <0>; + }; + + v1v8_audio:ldo1{ + regulator-name = "v1v8_audio"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + interrupts = ; + }; + + v3v3_hdmi:ldo2{ + regulator-name = "v3v3_hdmi"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + interrupts = ; + }; + vtt_ddr:ldo3{ + regulator-name = "vtt_ddr"; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <750000>; + regulator-always-on; + regulator-over-current-protection; + }; + + vdd_usb:ldo4{ + regulator-name = "vdd_usb"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + interrupts = ; + regulator-always-on; + }; + + vdda:ldo5{ + regulator-name = "vdda"; + regulator-min-microvolt = <2900000>; + regulator-max-microvolt = <2900000>; + interrupts = ; + regulator-boot-on; + }; + + v1v2_hdmi:ldo6{ + regulator-name = "v1v2_hdmi"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + interrupts = ; + }; + + vref_ddr:vref_ddr{ + regulator-name = "vref_ddr"; + regulator-always-on; + regulator-over-current-protection; + }; + + bst_out:boost{ + regulator-name = "bst_out"; + interrupts = ; + }; + + vbus_otg:pwr_sw1{ + regulator-name = "vbus_otg"; + interrupts = ; + }; + + vbus_sw:pwr_sw2{ + regulator-name = "vbus_sw"; + interrupts = ; + regulator-active-discharge = <1>; + }; + }; + + onkey{ + compatible = "st,stpmic1-onkey"; + interrupts = , ; + interrupt-names = "onkey-falling", "onkey-rising"; + power-off-time-sec = <10>; + status = "okay"; + }; + + watchdog { + compatible = "st,stpmic1-wdt"; + status = "disabled"; + }; + }; + /* USER CODE END i2c4 */ +}; + +&i2s2{ + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&i2s2_pins_mx>; + pinctrl-1 = <&i2s2_sleep_pins_mx>; + status = "okay"; + + /* USER CODE BEGIN i2s2 */ + clocks = <&rcc SPI2>, <&rcc SPI2_K>, <&rcc PLL3_Q>, <&rcc PLL3_R>; + clock-names = "pclk", "i2sclk", "x8k", "x11k"; + + i2s2_port:port{ + + i2s2_endpoint:endpoint{ + remote-endpoint = <&sii9022_tx_endpoint>; + format = "i2s"; + mclk-fs = <256>; + }; + }; + /* USER CODE END i2s2 */ +}; + +&ipcc{ + status = "okay"; + + /* USER CODE BEGIN ipcc */ + /* USER CODE END ipcc */ +}; + +&iwdg2{ + status = "okay"; + + /* USER CODE BEGIN iwdg2 */ + timeout-sec = <32>; + /* USER CODE END iwdg2 */ +}; + +<dc{ + status = "okay"; + + /* USER CODE BEGIN ltdc */ + + port{ + #address-cells = <1>; + #size-cells = <0>; + + ltdc_ep0_out:endpoint@0{ + reg = <0>; + remote-endpoint = <&sii9022_in>; + }; + + ltdc_ep1_out:endpoint@1{ + reg = <1>; + remote-endpoint = <&dsi_in>; + }; + }; + /* USER CODE END ltdc */ +}; + +&mdma1{ + status = "okay"; + + /* USER CODE BEGIN mdma1 */ + /* USER CODE END mdma1 */ +}; + +&pwr_regulators{ + status = "okay"; + + /* USER CODE BEGIN pwr_regulators */ + vdd-supply = <&vdd>; + vdd_3v3_usbfs-supply = <&vdd_usb>; + /* USER CODE END pwr_regulators */ +}; + +&rcc{ + u-boot,dm-pre-reloc; + status = "okay"; + + /* USER CODE BEGIN rcc */ + /* USER CODE END rcc */ +}; + +&rng1{ + status = "okay"; + + /* USER CODE BEGIN rng1 */ + /* USER CODE END rng1 */ +}; + +&rtc{ + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&rtc_pins_mx>; + pinctrl-1 = <&rtc_sleep_pins_mx>; + status = "okay"; + + /* USER CODE BEGIN rtc */ + st,lsco = ; + /* USER CODE END rtc */ +}; + +&sai2{ + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sai2a_pins_mx>, <&sai2b_pins_mx>; + pinctrl-1 = <&sai2a_sleep_pins_mx>, <&sai2b_sleep_pins_mx>; + status = "okay"; + + /* USER CODE BEGIN sai2 */ + clocks = <&rcc SAI2>, <&rcc PLL3_Q>, <&rcc PLL3_R>; + clock-names = "pclk", "x8k", "x11k"; + /* USER CODE END sai2 */ + + sai2a:audio-controller@4400b004{ + status = "okay"; + + /* USER CODE BEGIN sai2a */ + #clock-cells = <0>; + dma-names = "tx"; + clocks = <&rcc SAI2_K>; + clock-names = "sai_ck"; + + sai2a_port:port{ + + sai2a_endpoint:endpoint{ + remote-endpoint = <&cs42l51_tx_endpoint>; + format = "i2s"; + mclk-fs = <256>; + dai-tdm-slot-num = <2>; + dai-tdm-slot-width = <32>; + }; + }; + /* USER CODE END sai2a */ + }; + + sai2b:audio-controller@4400b024{ + status = "okay"; + + /* USER CODE BEGIN sai2b */ + dma-names = "rx"; + st,sync = <&sai2a 2>; + clocks = <&rcc SAI2_K>, <&sai2a>; + clock-names = "sai_ck", "MCLK"; + + sai2b_port:port{ + + sai2b_endpoint:endpoint{ + remote-endpoint = <&cs42l51_rx_endpoint>; + format = "i2s"; + mclk-fs = <256>; + dai-tdm-slot-num = <2>; + dai-tdm-slot-width = <32>; + }; + }; + /* USER CODE END sai2b */ + }; +}; + + + +&spi5{ + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&spi5_pins_mx>; + pinctrl-1 = <&spi5_sleep_pins_mx>; + status = "okay"; + + /* USER CODE BEGIN spi5 */ + /* USER CODE END spi5 */ +}; + +&tamp{ + status = "okay"; + + /* USER CODE BEGIN tamp */ + /* USER CODE END tamp */ +}; + +&uart4{ + u-boot,dm-pre-reloc; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&uart4_pins_mx>; + pinctrl-1 = <&uart4_sleep_pins_mx>; + status = "okay"; + + /* USER CODE BEGIN uart4 */ + /delete-property/ dmas; + /delete-property/ dma-names; + /* USER CODE END uart4 */ +}; + +&usart2{ + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&usart2_pins_mx>; + pinctrl-1 = <&usart2_sleep_pins_mx>; + status = "okay"; + + /* USER CODE BEGIN usart2 */ + uart-has-rtscts; + + bluetooth{ + shutdown-gpios = <&gpioz 6 GPIO_ACTIVE_HIGH>; + compatible = "brcm,bcm43438-bt"; + max-speed = <3000000>; + vbat-supply = <&v3v3>; + vddio-supply = <&v3v3>; + }; + /* USER CODE END usart2 */ +}; + +/* Added by mirika @SDT */ +#if 0 +&usart3{ + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&usart3_pins_mx>; + pinctrl-1 = <&usart3_sleep_pins_mx>; + status = "okay"; + + /* USER CODE BEGIN usart3 */ + /* USER CODE END usart3 */ +}; +#endif + +&usbh_ehci{ + status = "okay"; + + /* USER CODE BEGIN usbh_ehci */ + phys = <&usbphyc_port0>; + /* USER CODE END usbh_ehci */ +}; + +&usbh_ohci{ + status = "okay"; + + /* USER CODE BEGIN usbh_ohci */ + /* USER CODE END usbh_ohci */ +}; + +&usbotg_hs{ + u-boot,dm-pre-reloc; + status = "okay"; + + /* USER CODE BEGIN usbotg_hs */ + phys = <&usbphyc_port1 0>; + phy-names = "usb2-phy"; + usb-role-switch; + + port{ + + usbotg_hs_ep:endpoint{ + remote-endpoint = <&con_usbotg_hs_ep>; + }; + }; + /* USER CODE END usbotg_hs */ +}; + +&usbphyc{ + u-boot,dm-pre-reloc; + status = "okay"; + + /* USER CODE BEGIN usbphyc */ + /* USER CODE END usbphyc */ +}; + +&usbphyc_port0{ + u-boot,dm-pre-reloc; + status = "okay"; + + /* USER CODE BEGIN usbphyc_port0 */ + phy-supply = <&vdd_usb>; + st,phy-tuning = <&usb_phy_tuning>; + /* USER CODE END usbphyc_port0 */ +}; + +&usbphyc_port1{ + u-boot,dm-pre-reloc; + status = "okay"; + + /* USER CODE BEGIN usbphyc_port1 */ + phy-supply = <&vdd_usb>; + st,phy-tuning = <&usb_phy_tuning>; + /* USER CODE END usbphyc_port1 */ +}; + +&vrefbuf{ + status = "okay"; + + /* USER CODE BEGIN vrefbuf */ + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + vdda-supply = <&vdd>; + /* USER CODE END vrefbuf */ +}; + +/* USER CODE BEGIN addons */ +&adc { + status = "disabled"; +}; + +&usbh_ohci{ + phys = <&usbphyc_port0>; +}; + +&cpu0{ + cpu-supply = <&vddcore>; +}; + +&cpu1{ + cpu-supply = <&vddcore>; +}; + +&sram{ + + dma_pool:dma_pool@0{ + reg = <0x50000 0x10000>; + pool; + }; +}; + +&optee{ + status = "okay"; +}; + +&sdmmc1{ + u-boot,dm-pre-reloc; + pinctrl-names = "default", "opendrain", "sleep"; + pinctrl-0 = <&sdmmc1_pins_mx>; + pinctrl-1 = <&sdmmc1_opendrain_pins_mx>; + pinctrl-2 = <&sdmmc1_sleep_pins_mx>; + status = "okay"; + + /* USER CODE BEGIN sdmmc1 */ + cd-gpios = <&gpiob 7 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; + disable-wp; + st,neg-edge; + bus-width = <4>; + vmmc-supply = <&v3v3>; + /* USER CODE END sdmmc1 */ +}; + +/* eMMC */ +&sdmmc2 { + pinctrl-names = "default","opendrain","sleep"; + pinctrl-0 = <&sdmmc2_pins_mx>; + pinctrl-1 = <&sdmmc2_opendrain_pins_mx>; + pinctrl-2 = <&sdmmc2_sleep_pins_mx>; + non-removable; + no-sd; + no-sdio; + st,neg-edge; + bus-width = <4>; //bus-width 4 사용이면 4로 변경 + vmmc-supply = <&v3v3>; + vqmmc-supply = <&vdd>; + mmc-ddr-3_3v; + status = "okay"; +}; + +/* USER CODE END addons */ + diff --git a/meta-st/meta-st-stm32mpu-hce/recipes-aws/greengrass/greengrass.inc b/meta-st/meta-st-stm32mpu-hce/recipes-aws/greengrass/greengrass.inc new file mode 100644 index 0000000..a56d87a --- /dev/null +++ b/meta-st/meta-st-stm32mpu-hce/recipes-aws/greengrass/greengrass.inc @@ -0,0 +1,96 @@ +SUMMARY = "AWS IoT Greengrass Core Recipe" +DESCRIPTION = "AWS IoT Greengrass seamlessly extends AWS to edge devices so \ + they can act locally on the data they generate, while \ + still using the cloud for management, analytics, and durable \ + storage. With AWS IoT Greengrass, connected devices can run \ + AWS Lambda functions, Docker containers, or both, \ + execute predictions based on machine learning models, keep \ + device data in sync, and communicate with other devices \ + securely – even when not connected to the Internet." + +S = "${WORKDIR}/${BPN}" + +inherit update-rc.d systemd + +GG_USESYSTEMD = "${@bb.utils.contains('DISTRO_FEATURES', 'systemd', 'yes', 'no', d)}" + +# Disable tasks not needed for the binary package +do_configure[noexec] = "1" +do_compile[noexec] = "1" + +do_install() { + install -d ${D}/${BPN} + tar --no-same-owner --exclude='./patches' --exclude='./.pc' -cpf - -C ${S} . \ + | tar --no-same-owner -xpf - -C ${D}/${BPN} + + # Install wrapper bootscript to launch Greengrass core on boot + install -d ${D}${sysconfdir}/init.d + install -m 0755 ${WORKDIR}/greengrass-init ${D}${sysconfdir}/greengrass + sed -i -e "s,##GG_INSTALL_DIR##,/${BPN},g" ${D}${sysconfdir}/greengrass + ln -sf ${sysconfdir}/greengrass ${D}${sysconfdir}/init.d/greengrass + + # Install systemd service + install -d ${D}${systemd_unitdir}/system/ + install -m 0644 ${WORKDIR}/greengrass.service ${D}${systemd_unitdir}/system/greengrass.service + + # Configure whether to use systemd or not + sed -i -e "/useSystemd/{s,\[yes|no],${GG_USESYSTEMD},g}" ${D}/${BPN}/config/config.json +} + +pkg_postinst_ontarget_${PN}() { + # Enable protection for hardlinks and symlinks + if ! grep -qs 'protected_.*links' $D${sysconfdir}/sysctl.conf | grep -v '^#'; then + cat >> $D${sysconfdir}/sysctl.conf <<-_EOF_ +# Greengrass: protect hardlinks/symlinks +fs.protected_hardlinks = 1 +fs.protected_symlinks = 1 +_EOF_ + fi + + # Customize '/etc/fstab' + if [ -f "$D${sysconfdir}/fstab" ]; then + # Disable TMPFS /var/volatile + sed -i -e '\#^tmpfs[[:blank:]]\+/var/volatile#s,^,#,g' $D${sysconfdir}/fstab + + # Mount a cgroup hierarchy with all available subsystems + if ! grep -qs '^cgroup' $D${sysconfdir}/fstab; then + cat >> $D${sysconfdir}/fstab <<-_EOF_ + # Greengrass: mount cgroups + cgroup /sys/fs/cgroup cgroup defaults 0 0 + _EOF_ + mount -at cgroup 2>/dev/null + fi + fi + + # Disable '/etc/resolv.conf' symlink + if [ -f "$D${sysconfdir}/default/volatiles/00_core" ]; then + sed -i -e '/resolv.conf/d' $D${sysconfdir}/default/volatiles/00_core + cat >> $D${sysconfdir}/default/volatiles/00_core <<-_EOF_ + # Greengrass: create a real (no symlink) resolv.conf + f root root 0644 /etc/resolv.conf none + _EOF_ + fi +} + +FILES_${PN} = "/${BPN} ${sysconfdir} ${systemd_unitdir}" + +CONFFILES_${PN} += "/${BPN}/config/config.json" + +INITSCRIPT_NAME = "greengrass" +INITSCRIPT_PARAMS = "defaults 80 20" + +SYSTEMD_SERVICE_${PN} = "greengrass.service" + +inherit useradd +USERADD_PACKAGES = "${PN}" +GROUPADD_PARAM_${PN} = "--system ggc_group" +USERADD_PARAM_${PN} = "--system --gid ggc_group --shell /bin/false ggc_user" + +# +# Disable failing QA checks: +# +# Binary was already stripped +# No GNU_HASH in the elf binary +# +INSANE_SKIP_${PN} += "already-stripped ldflags file-rdeps" + diff --git a/meta-st/meta-st-stm32mpu-hce/recipes-aws/greengrass/greengrass/config_secu_example.json b/meta-st/meta-st-stm32mpu-hce/recipes-aws/greengrass/greengrass/config_secu_example.json new file mode 100644 index 0000000..b753c57 --- /dev/null +++ b/meta-st/meta-st-stm32mpu-hce/recipes-aws/greengrass/greengrass/config_secu_example.json @@ -0,0 +1,35 @@ +{ + "coreThing": { + "thingArn": "[THING_ARN_HERE]", + "iotHost": "[HOST_PREFIX_HERE]-ats.iot.[AWS_REGION_HERE].amazonaws.com", + "ggHost": "greengrass-ats.iot.[AWS_REGION_HERE].amazonaws.com", + "keepAlive" : 600 + }, + "runtime": { + "cgroup": { + "useSystemd": "yes" + } + }, + "managedRespawn": false, + "crypto": { + "caPath" : "file:///greengrass/certs/root.ca.pem", + "PKCS11": { + "P11Provider": "/usr/lib/libtpm2_pkcs11.so.0", + "slotLabel": "greengrass", + "slotUserPin": "123456" + }, + "principals": { + "IoTCertificate": { + "privateKeyPath": "pkcs11:token=greengrass;object=greenkey;type=private;pin-value=123456", + "certificatePath": "file:///greengrass/certs/[xxxxxxxx-certificate.pem.crt]" + }, + "SecretsManager": { + "privateKeyPath": "pkcs11:token=greengrass;object=greenkey;type=private;pin-value=123456" + }, + "MQTTServerCertificate": { + "privateKeyPath": "pkcs11:token=greengrass;object=greenkey;type=private;pin-value=123456", + "certificatePath": "file:///greengrass/certs/[xxxxxxxx-certificate.pem.crt]" + } + } + } +} diff --git a/meta-st/meta-st-stm32mpu-hce/recipes-aws/greengrass/greengrass/greengrass-init b/meta-st/meta-st-stm32mpu-hce/recipes-aws/greengrass/greengrass/greengrass-init new file mode 100644 index 0000000..8ed4166 --- /dev/null +++ b/meta-st/meta-st-stm32mpu-hce/recipes-aws/greengrass/greengrass/greengrass-init @@ -0,0 +1,13 @@ +#!/bin/sh + +GG_LAUNCHER="$(find ##GG_INSTALL_DIR## -type f -name greengrassd)" + +case "${1}" in + start | stop | restart) + ${GG_LAUNCHER} ${1} + ;; + *) + echo "Usage: $0 {start|stop|restart}" + exit 1 + ;; +esac \ No newline at end of file diff --git a/meta-st/meta-st-stm32mpu-hce/recipes-aws/greengrass/greengrass/greengrass.service b/meta-st/meta-st-stm32mpu-hce/recipes-aws/greengrass/greengrass/greengrass.service new file mode 100644 index 0000000..71976e1 --- /dev/null +++ b/meta-st/meta-st-stm32mpu-hce/recipes-aws/greengrass/greengrass/greengrass.service @@ -0,0 +1,10 @@ +[Unit] +Description=Greengrass core daemon + +[Service] +Type=forking +ExecStart=/etc/greengrass start +ExecStop=/etc/greengrass stop + +[Install] +WantedBy=multi-user.target diff --git a/meta-st/meta-st-stm32mpu-hce/recipes-aws/greengrass/greengrass/tpm_update.sh b/meta-st/meta-st-stm32mpu-hce/recipes-aws/greengrass/greengrass/tpm_update.sh new file mode 100644 index 0000000..c39ced6 --- /dev/null +++ b/meta-st/meta-st-stm32mpu-hce/recipes-aws/greengrass/greengrass/tpm_update.sh @@ -0,0 +1,10 @@ +#!/bin/bash +mkdir /usr/local/pkcs11_tpm +cd /usr/lib +ln -sf libtss2-tcti-device.so.0.0.0 libtss2-tcti-device.so +ln -sf libtss2-tcti-tabrmd.so.0.0.0 libtss2-tcti-tabrmd.so +cd /usr/bin +ln -sf python3.8 python +export TPM2_PKCS11_STORE=/usr/local/pkcs11_tpm +sync +cd diff --git a/meta-st/meta-st-stm32mpu-hce/recipes-aws/greengrass/greengrass_1.11.0.bb b/meta-st/meta-st-stm32mpu-hce/recipes-aws/greengrass/greengrass_1.11.0.bb new file mode 100644 index 0000000..c67e76e --- /dev/null +++ b/meta-st/meta-st-stm32mpu-hce/recipes-aws/greengrass/greengrass_1.11.0.bb @@ -0,0 +1,33 @@ +require greengrass.inc + +LICENSE = "MIT" +LIC_FILES_CHKSUM = " \ + file://ggc/core/THIRD-PARTY-LICENSES;md5=d3fb176f85edb203d99ed157c1301989 \ +" + +SRC_URI_arm = " \ + https://d1onfpft10uf5o.cloudfront.net/greengrass-core/downloads/${PV}/greengrass-linux-armv7l-${PV}.tar.gz;name=arm \ + file://greengrass.service \ + file://greengrass-init \ + file://config_secu_example.json \ + file://tpm_update.sh \ +" + + +SRC_URI[arm.md5sum] = "c5f2981d724e200c0d68ee41e6f6b47c" +SRC_URI[arm.sha256sum] = "af6ac0b277193a17d59b010071e153aa3d9aca1136062dd044caab3a9b663b13" + + +# Release specific configuration + +do_install_append() { + install -m 0644 ${WORKDIR}/config_secu_example.json ${D}/greengrass/config/config_secu_example.json + install -m 0644 ${WORKDIR}/tpm_update.sh ${D}/greengrass/tpm_update.sh +} + +RDEPENDS_${PN} += "ca-certificates python3-json python3-numbers sqlite3" +RDEPENDS_${PN} += "opensc openssl libp11" + +INSANE_SKIP_${PN} += " libdir" + +FETCHCMD_wget = "/usr/bin/env wget -t 10 -T 30 --passive-ftp --no-check-certificate" diff --git a/meta-st/meta-st-stm32mpu-hce/recipes-aws/greengrasstests/greengrasstests.bb b/meta-st/meta-st-stm32mpu-hce/recipes-aws/greengrasstests/greengrasstests.bb new file mode 100644 index 0000000..be27666 --- /dev/null +++ b/meta-st/meta-st-stm32mpu-hce/recipes-aws/greengrasstests/greengrasstests.bb @@ -0,0 +1,31 @@ +SUMMARY = "AWS IoT Greengrass IDT" +HOMEPAGE = "https://aws.amazon.com/greengrass/" + + +LICENSE = "BSD-3-Clause" +LIC_FILES_CHKSUM = "file://${COREBASE}/meta/files/common-licenses/BSD-3-Clause;md5=550794465ba0ec5312d6919e203a55f9" + + +FILEEXTRAPATHS_prepend := "$(THISDIR)/$(PN):" + +SRC_URI = " \ + file://aws_certif_update.sh \ +" + + +S = "${WORKDIR}" + + +# Disable tasks not needed for the binary package +do_configure[noexec] = "1" +do_compile[noexec] = "1" + +do_install() { + install -d ${D}${base_libdir} + install -d ${D}/greengrass + install -m 0644 ${S}/aws_certif_update.sh ${D}/greengrass/ +} + +RDEPENDS_${PN} = "bash" + +FILES_${PN} = "/greengrass/aws_certif_update.sh" diff --git a/meta-st/meta-st-stm32mpu-hce/recipes-aws/greengrasstests/greengrasstests/aws_certif_update.sh b/meta-st/meta-st-stm32mpu-hce/recipes-aws/greengrasstests/greengrasstests/aws_certif_update.sh new file mode 100644 index 0000000..06410d3 --- /dev/null +++ b/meta-st/meta-st-stm32mpu-hce/recipes-aws/greengrasstests/greengrasstests/aws_certif_update.sh @@ -0,0 +1,5 @@ +#!/bin/bash +cd +echo 'SetEnv "TPM2_PKCS11_STORE=/usr/local/pkcs11_tpm"' >> /etc/ssh/sshd_config +mkdir /home/root/.ssh +sync diff --git a/meta-st/meta-st-stm32mpu-hce/recipes-aws/greengrasstests/greengrasstests/device-hsm.json b/meta-st/meta-st-stm32mpu-hce/recipes-aws/greengrasstests/greengrasstests/device-hsm.json new file mode 100644 index 0000000..a26714e --- /dev/null +++ b/meta-st/meta-st-stm32mpu-hce/recipes-aws/greengrasstests/greengrasstests/device-hsm.json @@ -0,0 +1,41 @@ +[ + { + "id": "", + "sku": "STM32MP157C-DK2-TPM", + "features": [ + { + "name": "os", + "value": "linux" + }, + { + "name": "arch", + "value": "armv7l" + } + ], + "hsm": { + "p11Provider": "/usr/lib/libtpm2_pkcs11.so.0", + "slotLabel": "greengrass", + "slotUserPin": "123456", + "privateKeyLabel": "greenkey", + "openSSLEngine": "/usr/lib/engines-1.1/pkcs11.so" + }, + "kernelConfigLocation": "", + "greengrassLocation": "/greengrass", + "devices": [ + { + "id": "", + "connectivity": { + "protocol": "ssh", + "ip": "", + "auth": { + "method": "pki", + "credentials": { + "user": "root", + "privKeyPath": "/home//.ssh/id_rsa" + } + } + } + } + ] + } +] diff --git a/meta-st/meta-st-stm32mpu-hce/recipes-bsp/u-boot/u-boot-stm32mp/0001-If-a-devices-Main-Power-is-used-external-power-sourc.patch b/meta-st/meta-st-stm32mpu-hce/recipes-bsp/u-boot/u-boot-stm32mp/0001-If-a-devices-Main-Power-is-used-external-power-sourc.patch new file mode 100644 index 0000000..4ecb13f --- /dev/null +++ b/meta-st/meta-st-stm32mpu-hce/recipes-bsp/u-boot/u-boot-stm32mp/0001-If-a-devices-Main-Power-is-used-external-power-sourc.patch @@ -0,0 +1,33 @@ +From e95aa0076313ed818b6b78cc1d5345dae2770731 Mon Sep 17 00:00:00 2001 +From: mirikaKang +Date: Tue, 29 Jun 2021 17:33:16 +0900 +Subject: [PATCH] If a devices Main Power is used external power source instead + USB Power source + +--- + board/st/stm32mp1/stm32mp1.c | 11 +++++++++-- + 1 file changed, 9 insertions(+), 2 deletions(-) + +diff --git a/board/st/stm32mp1/stm32mp1.c b/board/st/stm32mp1/stm32mp1.c +index 617d05d209..f96575e41c 100644 +--- a/board/st/stm32mp1/stm32mp1.c ++++ b/board/st/stm32mp1/stm32mp1.c +@@ -490,9 +490,16 @@ static int board_check_usb_power(void) + pr_err("* Current too low, use a 3A power supply! *\n"); + pr_err("****************************************************\n\n"); + } +- ++/* Added by SDT */ ++/* If a devices Main Power is used external power source instead USB Power source*/ ++#ifdef USED_USB_POWER + led_error_blink(nb_blink); +- ++#else ++ if( nb_blink == U32_MAX ) ++ pr_info("This Device Used External PowerSource\n"); ++ else ++ led_error_blink(nb_blink); ++#endif + return 0; + } + #endif /* CONFIG_ADC */ diff --git a/meta-st/meta-st-stm32mpu-hce/recipes-bsp/u-boot/u-boot-stm32mp_2020.01.bbappend b/meta-st/meta-st-stm32mpu-hce/recipes-bsp/u-boot/u-boot-stm32mp_2020.01.bbappend new file mode 100644 index 0000000..e434bbb --- /dev/null +++ b/meta-st/meta-st-stm32mpu-hce/recipes-bsp/u-boot/u-boot-stm32mp_2020.01.bbappend @@ -0,0 +1,4 @@ +FILESEXTRAPATHS_prepend := "${THISDIR}/${PN}:" + +SRC_URI += "file://0001-If-a-devices-Main-Power-is-used-external-power-sourc.patch" + diff --git a/meta-st/meta-st-stm32mpu-hce/recipes-kernel/linux/linux-stm32mp/5.4/0001-can-buffer-up-remove-debug-log-in-stc311x_battery.patch b/meta-st/meta-st-stm32mpu-hce/recipes-kernel/linux/linux-stm32mp/5.4/0001-can-buffer-up-remove-debug-log-in-stc311x_battery.patch new file mode 100644 index 0000000..c984cf8 --- /dev/null +++ b/meta-st/meta-st-stm32mpu-hce/recipes-kernel/linux/linux-stm32mp/5.4/0001-can-buffer-up-remove-debug-log-in-stc311x_battery.patch @@ -0,0 +1,188 @@ +From 48448ef3a0033cf78bc080b9024d0be6640b3c43 Mon Sep 17 00:00:00 2001 +From: mirikaKang +Date: Tue, 6 Jul 2021 21:43:39 +0900 +Subject: [PATCH] can buffer up, remove debug log in stc311x_battery + +--- + arch/arm/boot/dts/stm32mp153.dtsi | 4 ++-- + .../iio/imu/st_lsm6dsx/st_lsm6dsx_buffer.c | 5 ++++- + drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c | 19 +++++++++++++++++-- + drivers/power/supply/stc311x_battery.c | 11 +---------- + 4 files changed, 24 insertions(+), 15 deletions(-) + +diff --git a/arch/arm/boot/dts/stm32mp153.dtsi b/arch/arm/boot/dts/stm32mp153.dtsi +index cf16b843c..3e04ddabb 100644 +--- a/arch/arm/boot/dts/stm32mp153.dtsi ++++ b/arch/arm/boot/dts/stm32mp153.dtsi +@@ -34,7 +34,7 @@ + interrupt-names = "int0", "int1"; + clocks = <&scmi0_clk CK_SCMI0_HSE>, <&rcc FDCAN_K>; + clock-names = "hclk", "cclk"; +- bosch,mram-cfg = <0x0 0 0 32 0 0 2 2>; ++ bosch,mram-cfg = <0x0 0 0 64 0 0 2 2>; + status = "disabled"; + }; + +@@ -47,7 +47,7 @@ + interrupt-names = "int0", "int1"; + clocks = <&scmi0_clk CK_SCMI0_HSE>, <&rcc FDCAN_K>; + clock-names = "hclk", "cclk"; +- bosch,mram-cfg = <0x1400 0 0 32 0 0 2 2>; ++ bosch,mram-cfg = <0x1400 0 0 64 0 0 2 2>; + status = "disabled"; + }; + }; +diff --git a/drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_buffer.c b/drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_buffer.c +index b0f3da197..37bd5baa3 100644 +--- a/drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_buffer.c ++++ b/drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_buffer.c +@@ -56,7 +56,10 @@ + + #define ST_LSM6DSX_MAX_FIFO_ODR_VAL 0x08 + +-#define ST_LSM6DSX_TS_SENSITIVITY 25000UL /* 25us */ ++// #define ST_LSM6DSX_TS_SENSITIVITY 25000UL /* 25us */ ++// #define ST_LSM6DSX_TS_SENSITIVITY 5000UL /* 5us */ ++#define ST_LSM6DSX_TS_SENSITIVITY 100000UL /* 100us */ ++ + #define ST_LSM6DSX_TS_RESET_VAL 0xaa + + struct st_lsm6dsx_decimator_entry { +diff --git a/drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c b/drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c +index 057a4b010..fe6673b87 100644 +--- a/drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c ++++ b/drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c +@@ -58,6 +58,9 @@ + + #include "st_lsm6dsx.h" + ++/* ADD by SDT */ ++#define DEFAULT_ODR_SDT 416 ++ + #define ST_LSM6DSX_REG_FIFO_FTH_IRQ_MASK BIT(3) + #define ST_LSM6DSX_REG_WHOAMI_ADDR 0x0f + #define ST_LSM6DSX_REG_RESET_MASK BIT(0) +@@ -1014,6 +1017,7 @@ static int st_lsm6dsx_set_odr(struct st_lsm6dsx_sensor *sensor, u16 req_odr) + u8 val = 0; + int err; + ++ + switch (sensor->id) { + case ST_LSM6DSX_ID_EXT0: + case ST_LSM6DSX_ID_EXT1: +@@ -1062,7 +1066,8 @@ int st_lsm6dsx_sensor_set_enable(struct st_lsm6dsx_sensor *sensor, + u16 odr = enable ? sensor->odr : 0; + int err; + +- err = st_lsm6dsx_set_odr(sensor, odr); ++ /* Modified by SDT */ ++ err = st_lsm6dsx_set_odr(sensor, DEFAULT_ODR_SDT); + if (err < 0) + return err; + +@@ -1081,11 +1086,15 @@ static int st_lsm6dsx_read_oneshot(struct st_lsm6dsx_sensor *sensor, + int err, delay; + __le16 data; + ++ ++ + err = st_lsm6dsx_sensor_set_enable(sensor, true); + if (err < 0) + return err; + + delay = 1000000 / sensor->odr; ++ ++ + usleep_range(delay, 2 * delay); + + err = st_lsm6dsx_read_locked(hw, addr, &data, sizeof(data)); +@@ -1106,6 +1115,7 @@ static int st_lsm6dsx_read_raw(struct iio_dev *iio_dev, + struct st_lsm6dsx_sensor *sensor = iio_priv(iio_dev); + int ret; + ++ + switch (mask) { + case IIO_CHAN_INFO_RAW: + ret = iio_device_claim_direct_mode(iio_dev); +@@ -1113,6 +1123,7 @@ static int st_lsm6dsx_read_raw(struct iio_dev *iio_dev, + break; + + ret = st_lsm6dsx_read_oneshot(sensor, ch->address, val); ++ + iio_device_release_direct_mode(iio_dev); + break; + case IIO_CHAN_INFO_SAMP_FREQ: +@@ -1205,6 +1216,10 @@ st_lsm6dsx_sysfs_sampling_frequency_avail(struct device *dev, + hw->settings->odr_table[id].odr_avl[i].hz); + buf[len - 1] = '\n'; + ++ /* Debug */ ++ dev_info(hw->dev, "[%s:%d] ---------- %s \n",__FUNCTION__,__LINE__,buf); ++ /* */ ++ + return len; + } + +@@ -1353,7 +1368,7 @@ static int st_lsm6dsx_init_hw_timer(struct st_lsm6dsx_hw *hw) + { + const struct st_lsm6dsx_hw_ts_settings *ts_settings; + int err, val; +- ++ + ts_settings = &hw->settings->ts_settings; + /* enable hw timestamp generation if necessary */ + if (ts_settings->timer_en.addr) { +diff --git a/drivers/power/supply/stc311x_battery.c b/drivers/power/supply/stc311x_battery.c +index 91bb4b355..c8e03fe38 100644 +--- a/drivers/power/supply/stc311x_battery.c ++++ b/drivers/power/supply/stc311x_battery.c +@@ -2256,16 +2256,13 @@ static int stc311x_battery_probe(struct i2c_client *client, + + + +- dev_dbg(&client->dev, "[%s:%d]STC311x probe started ************************************\n",__FUNCTION__,__LINE__); +- +- + /*First check the functionality supported by the host*/ + if (!i2c_check_functionality(adapter, I2C_FUNC_SMBUS_READ_I2C_BLOCK)) + return -EIO; + if (!i2c_check_functionality(adapter, I2C_FUNC_SMBUS_WRITE_I2C_BLOCK)) + return -EIO; + +- dev_info(&client->dev, "[%s:%d]STC311x Debug -------------------------------\n",__FUNCTION__,__LINE__); ++ + + /*OK. For now, we presume we have a valid client. We now create the + client structure*/ +@@ -2280,7 +2277,6 @@ static int stc311x_battery_probe(struct i2c_client *client, + /* The common I2C client data is placed right specific data. */ + chip->client = client; //copy pointer for I2C_read/I2C_write + +- dev_info(&client->dev, "[%s:%d]STC311x Debug -------------------------------\n",__FUNCTION__,__LINE__); + + #ifdef CONFIG_OF + printk("driver enabled from Linux Device Tree (DT)\n"); +@@ -2316,8 +2312,6 @@ static int stc311x_battery_probe(struct i2c_client *client, + stc311x_data_init(chip->stc311x_data); //init STC3117 data with Battery parameters + + } +- dev_info(&client->dev, "[%s:%d]STC311x Debug -------------------------------\n",__FUNCTION__,__LINE__); +- + i2c_set_clientdata(client, chip); + + +@@ -2439,11 +2433,8 @@ static int stc311x_battery_probe(struct i2c_client *client, + kfree(chip); + return -1; + } +- dev_info(&client->dev, "[%s:%d]STC311x Debug -------------------------------\n",__FUNCTION__,__LINE__); +- + GasGauge_Start(&GasGaugeData); + msleep(200); +- dev_info(&client->dev, "[%s:%d]STC311x Debug -------------------------------\n",__FUNCTION__,__LINE__); + res=GasGauge_Task(&GasGaugeData); /* process gas gauge algorithm, returns results */ + if (res>0) + { +-- +2.17.1 + diff --git a/meta-st/meta-st-stm32mpu-hce/recipes-kernel/linux/linux-stm32mp_%.bbappend b/meta-st/meta-st-stm32mpu-hce/recipes-kernel/linux/linux-stm32mp_%.bbappend new file mode 100644 index 0000000..3cc673a --- /dev/null +++ b/meta-st/meta-st-stm32mpu-hce/recipes-kernel/linux/linux-stm32mp_%.bbappend @@ -0,0 +1,9 @@ +# Configure recipe for CubeMX + +FILESEXTRAPATHS_prepend := "${THISDIR}/${PN}:" + + + + +# Patch +# SRC_URI += "file://5.4/0001-linux-commit-add-battery-driver-and-change-usb-seria.patch" diff --git a/meta-st/meta-st-stm32mpu-hce/recipes-kernel/max3109-test/files/Makefile b/meta-st/meta-st-stm32mpu-hce/recipes-kernel/max3109-test/files/Makefile new file mode 100644 index 0000000..6c79e75 --- /dev/null +++ b/meta-st/meta-st-stm32mpu-hce/recipes-kernel/max3109-test/files/Makefile @@ -0,0 +1,16 @@ +obj-m += max3109test.o + +SRC := $(shell pwd) + +all: + $(MAKE) -C $(KERNEL_SRC) M=$(SRC) modules + +modules_install: + $(MAKE) -C $(KERNEL_SRC) M=$(SRC) modules_install +kernel_clean: + $(MAKE) -C $(KERNEL_SRC) M=$(PWD) clean + +clean: kernel_clean + rm -rf Module.symvers modules.order +# clean: +# rm *.o \ No newline at end of file diff --git a/meta-st/meta-st-stm32mpu-hce/recipes-kernel/max3109-test/files/max3109test.c b/meta-st/meta-st-stm32mpu-hce/recipes-kernel/max3109-test/files/max3109test.c new file mode 100755 index 0000000..b0434ac --- /dev/null +++ b/meta-st/meta-st-stm32mpu-hce/recipes-kernel/max3109-test/files/max3109test.c @@ -0,0 +1,1696 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Maxim (Dallas) MAX3107/8/9, MAX14830 serial driver + * + * Copyright (C) 2012-2016 Alexander Shiyan + * + * Based on max3100.c, by Christian Pellegrin + * Based on max3110.c, by Feng Tang + * Based on max3107.c, by Aavamobile + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define MAX310X_NAME "max310x" +#define MAX310X_MAJOR 204 +#define MAX310X_MINOR 209 +#define MAX310X_UART_NRMAX 16 + +/* MAX310X register definitions */ +#define MAX310X_RHR_REG (0x00) /* RX FIFO */ +#define MAX310X_THR_REG (0x00) /* TX FIFO */ +#define MAX310X_IRQEN_REG (0x01) /* IRQ enable */ +#define MAX310X_IRQSTS_REG (0x02) /* IRQ status */ +#define MAX310X_LSR_IRQEN_REG (0x03) /* LSR IRQ enable */ +#define MAX310X_LSR_IRQSTS_REG (0x04) /* LSR IRQ status */ +#define MAX310X_REG_05 (0x05) +#define MAX310X_SPCHR_IRQEN_REG MAX310X_REG_05 /* Special char IRQ en */ +#define MAX310X_SPCHR_IRQSTS_REG (0x06) /* Special char IRQ status */ +#define MAX310X_STS_IRQEN_REG (0x07) /* Status IRQ enable */ +#define MAX310X_STS_IRQSTS_REG (0x08) /* Status IRQ status */ +#define MAX310X_MODE1_REG (0x09) /* MODE1 */ +#define MAX310X_MODE2_REG (0x0a) /* MODE2 */ +#define MAX310X_LCR_REG (0x0b) /* LCR */ +#define MAX310X_RXTO_REG (0x0c) /* RX timeout */ +#define MAX310X_HDPIXDELAY_REG (0x0d) /* Auto transceiver delays */ +#define MAX310X_IRDA_REG (0x0e) /* IRDA settings */ +#define MAX310X_FLOWLVL_REG (0x0f) /* Flow control levels */ +#define MAX310X_FIFOTRIGLVL_REG (0x10) /* FIFO IRQ trigger levels */ +#define MAX310X_TXFIFOLVL_REG (0x11) /* TX FIFO level */ +#define MAX310X_RXFIFOLVL_REG (0x12) /* RX FIFO level */ +#define MAX310X_FLOWCTRL_REG (0x13) /* Flow control */ +#define MAX310X_XON1_REG (0x14) /* XON1 character */ +#define MAX310X_XON2_REG (0x15) /* XON2 character */ +#define MAX310X_XOFF1_REG (0x16) /* XOFF1 character */ +#define MAX310X_XOFF2_REG (0x17) /* XOFF2 character */ +#define MAX310X_GPIOCFG_REG (0x18) /* GPIO config */ +#define MAX310X_GPIODATA_REG (0x19) /* GPIO data */ +#define MAX310X_PLLCFG_REG (0x1a) /* PLL config */ +#define MAX310X_BRGCFG_REG (0x1b) /* Baud rate generator conf */ +#define MAX310X_BRGDIVLSB_REG (0x1c) /* Baud rate divisor LSB */ +#define MAX310X_BRGDIVMSB_REG (0x1d) /* Baud rate divisor MSB */ +#define MAX310X_CLKSRC_REG (0x1e) /* Clock source */ +#define MAX310X_REG_1F (0x1f) + +#define MAX310X_REVID_REG MAX310X_REG_1F /* Revision ID */ + +#define MAX310X_GLOBALIRQ_REG MAX310X_REG_1F /* Global IRQ (RO) */ +#define MAX310X_GLOBALCMD_REG MAX310X_REG_1F /* Global Command (WO) */ + +/* Extended registers */ +#define MAX310X_REVID_EXTREG MAX310X_REG_05 /* Revision ID */ + +/* IRQ register bits */ +#define MAX310X_IRQ_LSR_BIT (1 << 0) /* LSR interrupt */ +#define MAX310X_IRQ_SPCHR_BIT (1 << 1) /* Special char interrupt */ +#define MAX310X_IRQ_STS_BIT (1 << 2) /* Status interrupt */ +#define MAX310X_IRQ_RXFIFO_BIT (1 << 3) /* RX FIFO interrupt */ +#define MAX310X_IRQ_TXFIFO_BIT (1 << 4) /* TX FIFO interrupt */ +#define MAX310X_IRQ_TXEMPTY_BIT (1 << 5) /* TX FIFO empty interrupt */ +#define MAX310X_IRQ_RXEMPTY_BIT (1 << 6) /* RX FIFO empty interrupt */ +#define MAX310X_IRQ_CTS_BIT (1 << 7) /* CTS interrupt */ + +/* LSR register bits */ +#define MAX310X_LSR_RXTO_BIT (1 << 0) /* RX timeout */ +#define MAX310X_LSR_RXOVR_BIT (1 << 1) /* RX overrun */ +#define MAX310X_LSR_RXPAR_BIT (1 << 2) /* RX parity error */ +#define MAX310X_LSR_FRERR_BIT (1 << 3) /* Frame error */ +#define MAX310X_LSR_RXBRK_BIT (1 << 4) /* RX break */ +#define MAX310X_LSR_RXNOISE_BIT (1 << 5) /* RX noise */ +#define MAX310X_LSR_CTS_BIT (1 << 7) /* CTS pin state */ + +/* Special character register bits */ +#define MAX310X_SPCHR_XON1_BIT (1 << 0) /* XON1 character */ +#define MAX310X_SPCHR_XON2_BIT (1 << 1) /* XON2 character */ +#define MAX310X_SPCHR_XOFF1_BIT (1 << 2) /* XOFF1 character */ +#define MAX310X_SPCHR_XOFF2_BIT (1 << 3) /* XOFF2 character */ +#define MAX310X_SPCHR_BREAK_BIT (1 << 4) /* RX break */ +#define MAX310X_SPCHR_MULTIDROP_BIT (1 << 5) /* 9-bit multidrop addr char */ + +/* Status register bits */ +#define MAX310X_STS_GPIO0_BIT (1 << 0) /* GPIO 0 interrupt */ +#define MAX310X_STS_GPIO1_BIT (1 << 1) /* GPIO 1 interrupt */ +#define MAX310X_STS_GPIO2_BIT (1 << 2) /* GPIO 2 interrupt */ +#define MAX310X_STS_GPIO3_BIT (1 << 3) /* GPIO 3 interrupt */ +#define MAX310X_STS_CLKREADY_BIT (1 << 5) /* Clock ready */ +#define MAX310X_STS_SLEEP_BIT (1 << 6) /* Sleep interrupt */ + +/* MODE1 register bits */ +#define MAX310X_MODE1_RXDIS_BIT (1 << 0) /* RX disable */ +#define MAX310X_MODE1_TXDIS_BIT (1 << 1) /* TX disable */ +#define MAX310X_MODE1_TXHIZ_BIT (1 << 2) /* TX pin three-state */ +#define MAX310X_MODE1_RTSHIZ_BIT (1 << 3) /* RTS pin three-state */ +#define MAX310X_MODE1_TRNSCVCTRL_BIT (1 << 4) /* Transceiver ctrl enable */ +#define MAX310X_MODE1_FORCESLEEP_BIT (1 << 5) /* Force sleep mode */ +#define MAX310X_MODE1_AUTOSLEEP_BIT (1 << 6) /* Auto sleep enable */ +#define MAX310X_MODE1_IRQSEL_BIT (1 << 7) /* IRQ pin enable */ + +/* MODE2 register bits */ +#define MAX310X_MODE2_RST_BIT (1 << 0) /* Chip reset */ +#define MAX310X_MODE2_FIFORST_BIT (1 << 1) /* FIFO reset */ +#define MAX310X_MODE2_RXTRIGINV_BIT (1 << 2) /* RX FIFO INT invert */ +#define MAX310X_MODE2_RXEMPTINV_BIT (1 << 3) /* RX FIFO empty INT invert */ +#define MAX310X_MODE2_SPCHR_BIT (1 << 4) /* Special chr detect enable */ +#define MAX310X_MODE2_LOOPBACK_BIT (1 << 5) /* Internal loopback enable */ +#define MAX310X_MODE2_MULTIDROP_BIT (1 << 6) /* 9-bit multidrop enable */ +#define MAX310X_MODE2_ECHOSUPR_BIT (1 << 7) /* ECHO suppression enable */ + +/* LCR register bits */ +#define MAX310X_LCR_LENGTH0_BIT (1 << 0) /* Word length bit 0 */ +#define MAX310X_LCR_LENGTH1_BIT (1 << 1) /* Word length bit 1 + * + * Word length bits table: + * 00 -> 5 bit words + * 01 -> 6 bit words + * 10 -> 7 bit words + * 11 -> 8 bit words + */ +#define MAX310X_LCR_STOPLEN_BIT (1 << 2) /* STOP length bit + * + * STOP length bit table: + * 0 -> 1 stop bit + * 1 -> 1-1.5 stop bits if + * word length is 5, + * 2 stop bits otherwise + */ +#define MAX310X_LCR_PARITY_BIT (1 << 3) /* Parity bit enable */ +#define MAX310X_LCR_EVENPARITY_BIT (1 << 4) /* Even parity bit enable */ +#define MAX310X_LCR_FORCEPARITY_BIT (1 << 5) /* 9-bit multidrop parity */ +#define MAX310X_LCR_TXBREAK_BIT (1 << 6) /* TX break enable */ +#define MAX310X_LCR_RTS_BIT (1 << 7) /* RTS pin control */ + +/* IRDA register bits */ +#define MAX310X_IRDA_IRDAEN_BIT (1 << 0) /* IRDA mode enable */ +#define MAX310X_IRDA_SIR_BIT (1 << 1) /* SIR mode enable */ + +/* Flow control trigger level register masks */ +#define MAX310X_FLOWLVL_HALT_MASK (0x000f) /* Flow control halt level */ +#define MAX310X_FLOWLVL_RES_MASK (0x00f0) /* Flow control resume level */ +#define MAX310X_FLOWLVL_HALT(words) ((words / 8) & 0x0f) +#define MAX310X_FLOWLVL_RES(words) (((words / 8) & 0x0f) << 4) + +/* FIFO interrupt trigger level register masks */ +#define MAX310X_FIFOTRIGLVL_TX_MASK (0x0f) /* TX FIFO trigger level */ +#define MAX310X_FIFOTRIGLVL_RX_MASK (0xf0) /* RX FIFO trigger level */ +#define MAX310X_FIFOTRIGLVL_TX(words) ((words / 8) & 0x0f) +#define MAX310X_FIFOTRIGLVL_RX(words) (((words / 8) & 0x0f) << 4) + +/* Flow control register bits */ +#define MAX310X_FLOWCTRL_AUTORTS_BIT (1 << 0) /* Auto RTS flow ctrl enable */ +#define MAX310X_FLOWCTRL_AUTOCTS_BIT (1 << 1) /* Auto CTS flow ctrl enable */ +#define MAX310X_FLOWCTRL_GPIADDR_BIT (1 << 2) /* Enables that GPIO inputs + * are used in conjunction with + * XOFF2 for definition of + * special character */ +#define MAX310X_FLOWCTRL_SWFLOWEN_BIT (1 << 3) /* Auto SW flow ctrl enable */ +#define MAX310X_FLOWCTRL_SWFLOW0_BIT (1 << 4) /* SWFLOW bit 0 */ +#define MAX310X_FLOWCTRL_SWFLOW1_BIT (1 << 5) /* SWFLOW bit 1 + * + * SWFLOW bits 1 & 0 table: + * 00 -> no transmitter flow + * control + * 01 -> receiver compares + * XON2 and XOFF2 + * and controls + * transmitter + * 10 -> receiver compares + * XON1 and XOFF1 + * and controls + * transmitter + * 11 -> receiver compares + * XON1, XON2, XOFF1 and + * XOFF2 and controls + * transmitter + */ +#define MAX310X_FLOWCTRL_SWFLOW2_BIT (1 << 6) /* SWFLOW bit 2 */ +#define MAX310X_FLOWCTRL_SWFLOW3_BIT (1 << 7) /* SWFLOW bit 3 + * + * SWFLOW bits 3 & 2 table: + * 00 -> no received flow + * control + * 01 -> transmitter generates + * XON2 and XOFF2 + * 10 -> transmitter generates + * XON1 and XOFF1 + * 11 -> transmitter generates + * XON1, XON2, XOFF1 and + * XOFF2 + */ + +/* PLL configuration register masks */ +#define MAX310X_PLLCFG_PREDIV_MASK (0x3f) /* PLL predivision value */ +#define MAX310X_PLLCFG_PLLFACTOR_MASK (0xc0) /* PLL multiplication factor */ + +/* Baud rate generator configuration register bits */ +#define MAX310X_BRGCFG_2XMODE_BIT (1 << 4) /* Double baud rate */ +#define MAX310X_BRGCFG_4XMODE_BIT (1 << 5) /* Quadruple baud rate */ + +/* Clock source register bits */ +#define MAX310X_CLKSRC_CRYST_BIT (1 << 1) /* Crystal osc enable */ +#define MAX310X_CLKSRC_PLL_BIT (1 << 2) /* PLL enable */ +#define MAX310X_CLKSRC_PLLBYP_BIT (1 << 3) /* PLL bypass */ +#define MAX310X_CLKSRC_EXTCLK_BIT (1 << 4) /* External clock enable */ +#define MAX310X_CLKSRC_CLK2RTS_BIT (1 << 7) /* Baud clk to RTS pin */ + +/* Global commands */ +#define MAX310X_EXTREG_ENBL (0xce) +#define MAX310X_EXTREG_DSBL (0xcd) + +/* Misc definitions */ +#define MAX310X_FIFO_SIZE (128) +#define MAX310x_REV_MASK (0xf8) +#define MAX310X_WRITE_BIT 0x80 + +/* MAX3107 specific */ +#define MAX3107_REV_ID (0xa0) + +/* MAX3109 specific */ +#define MAX3109_REV_ID (0xc0) + +/* MAX14830 specific */ +#define MAX14830_BRGCFG_CLKDIS_BIT (1 << 6) /* Clock Disable */ +#define MAX14830_REV_ID (0xb0) + +struct max310x_devtype { + char name[9]; + int nr; + u8 mode1; + int (*detect)(struct device *); + void (*power)(struct uart_port *, int); +}; + +struct max310x_one { + struct uart_port port; + struct work_struct tx_work; + struct work_struct md_work; + struct work_struct rs_work; + + u8 wr_header; + u8 rd_header; + u8 rx_buf[MAX310X_FIFO_SIZE]; +}; +#define to_max310x_port(_port) \ + container_of(_port, struct max310x_one, port) + +struct max310x_port { + struct max310x_devtype *devtype; + struct regmap *regmap; + struct clk *clk; +#ifdef CONFIG_GPIOLIB + struct gpio_chip gpio; +#endif + struct max310x_one p[0]; +}; + +static struct uart_driver max310x_uart = { + .owner = THIS_MODULE, + .driver_name = MAX310X_NAME, + .dev_name = "ttyMAX", + .major = MAX310X_MAJOR, + .minor = MAX310X_MINOR, + .nr = MAX310X_UART_NRMAX, +}; + +static DECLARE_BITMAP(max310x_lines, MAX310X_UART_NRMAX); +static void max310x_handle_tx(struct uart_port *port); + + +static u8 max310x_port_read(struct uart_port *port, u8 reg) +{ + struct max310x_port *s = dev_get_drvdata(port->dev); + unsigned int val = 0; + + regmap_read(s->regmap, port->iobase + reg, &val); + + return val; +} + +static void max310x_port_write(struct uart_port *port, u8 reg, u8 val) +{ + struct max310x_port *s = dev_get_drvdata(port->dev); + + regmap_write(s->regmap, port->iobase + reg, val); +} + +static void max310x_port_update(struct uart_port *port, u8 reg, u8 mask, u8 val) +{ + struct max310x_port *s = dev_get_drvdata(port->dev); + + regmap_update_bits(s->regmap, port->iobase + reg, mask, val); +} + +static int max3107_detect(struct device *dev) +{ + struct max310x_port *s = dev_get_drvdata(dev); + unsigned int val = 0; + int ret; + + ret = regmap_read(s->regmap, MAX310X_REVID_REG, &val); + if (ret) + return ret; + + if (((val & MAX310x_REV_MASK) != MAX3107_REV_ID)) { + dev_err(dev, + "%s ID 0x%02x does not match\n", s->devtype->name, val); + return -ENODEV; + } + + return 0; +} + +static int max3108_detect(struct device *dev) +{ + struct max310x_port *s = dev_get_drvdata(dev); + unsigned int val = 0; + int ret; + + /* MAX3108 have not REV ID register, we just check default value + * from clocksource register to make sure everything works. + */ + ret = regmap_read(s->regmap, MAX310X_CLKSRC_REG, &val); + if (ret) + return ret; + + if (val != (MAX310X_CLKSRC_EXTCLK_BIT | MAX310X_CLKSRC_PLLBYP_BIT)) { + dev_err(dev, "%s not present\n", s->devtype->name); + return -ENODEV; + } + + return 0; +} + +static int max3109_detect(struct device *dev) +{ + struct max310x_port *s = dev_get_drvdata(dev); + unsigned int val = 0; + int ret; + + ret = regmap_write(s->regmap, MAX310X_GLOBALCMD_REG, + MAX310X_EXTREG_ENBL); + if (ret) + return ret; + + regmap_read(s->regmap, MAX310X_REVID_EXTREG, &val); + regmap_write(s->regmap, MAX310X_GLOBALCMD_REG, MAX310X_EXTREG_DSBL); + if (((val & MAX310x_REV_MASK) != MAX3109_REV_ID)) { + dev_err(dev, + "%s ID 0x%02x does not match\n", s->devtype->name, val); + return -ENODEV; + } + + return 0; +} + +static void max310x_power(struct uart_port *port, int on) +{ + max310x_port_update(port, MAX310X_MODE1_REG, + MAX310X_MODE1_FORCESLEEP_BIT, + on ? 0 : MAX310X_MODE1_FORCESLEEP_BIT); + if (on) + msleep(50); +} + +static int max14830_detect(struct device *dev) +{ + struct max310x_port *s = dev_get_drvdata(dev); + unsigned int val = 0; + int ret; + + ret = regmap_write(s->regmap, MAX310X_GLOBALCMD_REG, + MAX310X_EXTREG_ENBL); + if (ret) + return ret; + + regmap_read(s->regmap, MAX310X_REVID_EXTREG, &val); + regmap_write(s->regmap, MAX310X_GLOBALCMD_REG, MAX310X_EXTREG_DSBL); + if (((val & MAX310x_REV_MASK) != MAX14830_REV_ID)) { + dev_err(dev, + "%s ID 0x%02x does not match\n", s->devtype->name, val); + return -ENODEV; + } + + return 0; +} + +static void max14830_power(struct uart_port *port, int on) +{ + max310x_port_update(port, MAX310X_BRGCFG_REG, + MAX14830_BRGCFG_CLKDIS_BIT, + on ? 0 : MAX14830_BRGCFG_CLKDIS_BIT); + if (on) + msleep(50); +} + +static const struct max310x_devtype max3107_devtype = { + .name = "MAX3107", + .nr = 1, + .mode1 = MAX310X_MODE1_AUTOSLEEP_BIT | MAX310X_MODE1_IRQSEL_BIT, + .detect = max3107_detect, + .power = max310x_power, +}; + +static const struct max310x_devtype max3108_devtype = { + .name = "MAX3108", + .nr = 1, + .mode1 = MAX310X_MODE1_AUTOSLEEP_BIT, + .detect = max3108_detect, + .power = max310x_power, +}; + +static const struct max310x_devtype max3109_devtype = { + .name = "MAX3109", + .nr = 2, + .mode1 = MAX310X_MODE1_AUTOSLEEP_BIT, + .detect = max3109_detect, + .power = max310x_power, +}; + +static const struct max310x_devtype max14830_devtype = { + .name = "MAX14830", + .nr = 4, + .mode1 = MAX310X_MODE1_IRQSEL_BIT, + .detect = max14830_detect, + .power = max14830_power, +}; + +static bool max310x_reg_writeable(struct device *dev, unsigned int reg) +{ + switch (reg & 0x1f) { + case MAX310X_IRQSTS_REG: + case MAX310X_LSR_IRQSTS_REG: + case MAX310X_SPCHR_IRQSTS_REG: + case MAX310X_STS_IRQSTS_REG: + case MAX310X_TXFIFOLVL_REG: + case MAX310X_RXFIFOLVL_REG: + return false; + default: + break; + } + + return true; +} + +static bool max310x_reg_volatile(struct device *dev, unsigned int reg) +{ + switch (reg & 0x1f) { + case MAX310X_RHR_REG: + case MAX310X_IRQSTS_REG: + case MAX310X_LSR_IRQSTS_REG: + case MAX310X_SPCHR_IRQSTS_REG: + case MAX310X_STS_IRQSTS_REG: + case MAX310X_TXFIFOLVL_REG: + case MAX310X_RXFIFOLVL_REG: + case MAX310X_GPIODATA_REG: + case MAX310X_BRGDIVLSB_REG: + case MAX310X_REG_05: + case MAX310X_REG_1F: + return true; + default: + break; + } + + return false; +} + +static bool max310x_reg_precious(struct device *dev, unsigned int reg) +{ + switch (reg & 0x1f) { + case MAX310X_RHR_REG: + case MAX310X_IRQSTS_REG: + case MAX310X_SPCHR_IRQSTS_REG: + case MAX310X_STS_IRQSTS_REG: + return true; + default: + break; + } + + return false; +} + +static int max310x_set_baud(struct uart_port *port, int baud) +{ + unsigned int mode = 0, div = 0, frac = 0, c = 0, F = 0; + + /* + * Calculate the integer divisor first. Select a proper mode + * in case if the requested baud is too high for the pre-defined + * clocks frequency. + */ + div = port->uartclk / baud; + if (div < 8) { + /* Mode x4 */ + c = 4; + mode = MAX310X_BRGCFG_4XMODE_BIT; + } else if (div < 16) { + /* Mode x2 */ + c = 8; + mode = MAX310X_BRGCFG_2XMODE_BIT; + } else { + c = 16; + } + + /* Calculate the divisor in accordance with the fraction coefficient */ + div /= c; + F = c*baud; + + /* Calculate the baud rate fraction */ + if (div > 0) + frac = (16*(port->uartclk % F)) / F; + else + div = 1; + + max310x_port_write(port, MAX310X_BRGDIVMSB_REG, div >> 8); + max310x_port_write(port, MAX310X_BRGDIVLSB_REG, div); + max310x_port_write(port, MAX310X_BRGCFG_REG, frac | mode); + + /* Return the actual baud rate we just programmed */ + return (16*port->uartclk) / (c*(16*div + frac)); +} + +static int max310x_update_best_err(unsigned long f, long *besterr) +{ + /* Use baudrate 115200 for calculate error */ + long err = f % (460800 * 16); + printk("max310x freq: %ld, besterr: %ld, err: %d\n", f, *besterr, err); + + if ((*besterr < 0) || (*besterr > err)) { + *besterr = err; + return 0; + } + + return 1; +} + +static int max310x_set_ref_clk(struct device *dev, struct max310x_port *s, + unsigned long freq, bool xtal) +{ + unsigned int div, clksrc, pllcfg = 0; + long besterr = -1; + unsigned long fdiv, fmul, bestfreq = freq; + + /* First, update error without PLL */ + printk(KERN_DEBUG "max310x: %s: %lu Hz\n", dev_name(dev),freq); + max310x_update_best_err(freq, &besterr); + + // bestfreq = 3686400; + // printk("forced setting: max310x bestfreq: %ld, besterr: %ld\n", bestfreq, besterr); + /* Try all possible PLL dividers */ + for (div = 1; (div <= 63) && besterr; div++) { + fdiv = DIV_ROUND_CLOSEST(freq, div); + + /* Try multiplier 6 */ + fmul = fdiv * 6; + printk("%d: div(%d), fmul = %ld\n", __LINE__, div, fmul); + if ((fdiv >= 500000) && (fdiv <= 800000)) + if (!max310x_update_best_err(fmul, &besterr)) { + pllcfg = (0 << 6) | div; + bestfreq = fmul; + printk(KERN_DEBUG "max310x: %s: PLL: %lu Hz\n", + dev_name(dev), bestfreq); + } + printk("%d: div(%d), update besterr = %d, \n", __LINE__, div, max310x_update_best_err(fmul, &besterr)); + /* Try multiplier 48 */ + fmul = fdiv * 48; + if ((fdiv >= 850000) && (fdiv <= 1200000)) + if (!max310x_update_best_err(fmul, &besterr)) { + pllcfg = (1 << 6) | div; + bestfreq = fmul; + printk(KERN_DEBUG "max310x: %s: PLL: %lu Hz\n", + dev_name(dev), bestfreq); + } + printk("%d: div(%d), update besterr = %d, \n", __LINE__, div, max310x_update_best_err(fmul, &besterr)); + // /* Try multiplier 96 */ + // fmul = fdiv * 96; + // if ((fdiv >= 425000) && (fdiv <= 1000000)) + // if (!max310x_update_best_err(fmul, &besterr)) { + // pllcfg = (2 << 6) | div; + // bestfreq = fmul; + // printk(KERN_DEBUG "max310x: %s: PLL: %lu Hz\n", + // dev_name(dev), bestfreq); + // } + // /* Try multiplier 144 */ + // fmul = fdiv * 144; + // if ((fdiv >= 390000) && (fdiv <= 667000)) + // if (!max310x_update_best_err(fmul, &besterr)) { + // pllcfg = (3 << 6) | div; + // bestfreq = fmul; + // printk(KERN_DEBUG "max310x: %s: PLL: %lu Hz\n", + // dev_name(dev), bestfreq); + // } + } + + printk("max310x bestfreq: %ld, besterr: %ld\n", bestfreq, besterr); + + /* Configure clock source */ + clksrc = MAX310X_CLKSRC_EXTCLK_BIT | (xtal ? MAX310X_CLKSRC_CRYST_BIT : 0); + + /* Configure PLL */ + if (pllcfg) { + clksrc |= MAX310X_CLKSRC_PLL_BIT; + regmap_write(s->regmap, MAX310X_PLLCFG_REG, pllcfg); + } else + clksrc |= MAX310X_CLKSRC_PLLBYP_BIT; + + regmap_write(s->regmap, MAX310X_CLKSRC_REG, clksrc); + + /* Wait for crystal */ + if (xtal) { + unsigned int val; + msleep(10); + regmap_read(s->regmap, MAX310X_STS_IRQSTS_REG, &val); + if (!(val & MAX310X_STS_CLKREADY_BIT)) { + dev_warn(dev, "clock is not stable yet\n"); + } + } + + return (int)bestfreq; +} + +static void max310x_batch_write(struct uart_port *port, u8 *txbuf, unsigned int len) +{ + struct max310x_one *one = to_max310x_port(port); + + struct spi_transfer xfer[] = { + { + .tx_buf = &one->wr_header, + .len = sizeof(one->wr_header), + }, { + .tx_buf = txbuf, + .len = len, + } + }; + + struct max310x_port *s = dev_get_drvdata(port->dev); + + struct uart_port *port1 = &s->p[0].port; + struct uart_port *port2 = &s->p[1].port; + unsigned int ists1, ists2, glob1, glob2; + glob1 = max310x_port_read(port1, MAX310X_REG_1F); + glob2 = max310x_port_read(port2, MAX310X_REG_1F); + // printk("ists1: %x, ists2: %x\n", ists1, ists2); + // printk("glob1: %x, glob2: %x\n", glob1, glob2); + if(glob1 ==0 && glob2 == 0) + { + ists1 = max310x_port_read(port1, MAX310X_IRQSTS_REG); + ists2 = max310x_port_read(port2, MAX310X_IRQSTS_REG); + // printk("ists1: %x, ists2: %x\n", ists1, ists2); + } + // printk("ists1: %x\n", ists1); + // if(ists & 0x20) + // { + // printk("handle tx process \n"); + // max310x_handle_tx(port); + // } + spi_sync_transfer(to_spi_device(port->dev), xfer, ARRAY_SIZE(xfer)); + // printk("start tx txfifolen: %d\n", max310x_port_read(port, MAX310X_TXFIFOLVL_REG)); +} + +static void max310x_batch_read(struct uart_port *port, u8 *rxbuf, unsigned int len) +{ + // printk("batch read\n"); + struct max310x_one *one = to_max310x_port(port); + struct spi_transfer xfer[] = { + { + .tx_buf = &one->rd_header, + .len = sizeof(one->rd_header), + }, { + .rx_buf = rxbuf, + .len = len, + } + }; + + // unsigned int glob; + // ists1 = max310x_port_read(port1, MAX310X_IRQSTS_REG); + // ists2 = max310x_port_read(port2, MAX310X_IRQSTS_REG); + // glob = max310x_port_read(port, MAX310X_REG_1F); + // glob2 = max310x_port_read(port2, MAX310X_REG_1F); + // printk("ists1: %x, ists2: %x\n", ists1, ists2); + // printk("glob: %x\n", glob); + + spi_sync_transfer(to_spi_device(port->dev), xfer, ARRAY_SIZE(xfer)); +} + +static void max310x_handle_rx(struct uart_port *port, unsigned int rxlen) +{ + struct max310x_one *one = to_max310x_port(port); + unsigned int sts, ch, flag, i; + + unsigned int total_recv; + total_recv = 0; + if (port->read_status_mask == MAX310X_LSR_RXOVR_BIT) { + /* We are just reading, happily ignoring any error conditions. + * Break condition, parity checking, framing errors -- they + * are all ignored. That means that we can do a batch-read. + * + * There is a small opportunity for race if the RX FIFO + * overruns while we're reading the buffer; the datasheets says + * that the LSR register applies to the "current" character. + * That's also the reason why we cannot do batched reads when + * asked to check the individual statuses. + * */ + + sts = max310x_port_read(port, MAX310X_LSR_IRQSTS_REG); + max310x_batch_read(port, one->rx_buf, rxlen); + + port->icount.rx += rxlen; + total_recv += rxlen; + flag = TTY_NORMAL; + sts &= port->read_status_mask; + + if (sts & MAX310X_LSR_RXOVR_BIT) { + dev_warn_ratelimited(port->dev, "Hardware RX FIFO overrun\n"); + port->icount.overrun++; + printk("Hardware RX FIFO overrun (%d)\n",port->icount.overrun); + } + + for (i = 0; i < (rxlen - 1); ++i) + uart_insert_char(port, sts, 0, one->rx_buf[i], flag); + + /* + * Handle the overrun case for the last character only, since + * the RxFIFO overflow happens after it is pushed to the FIFO + * tail. + */ + uart_insert_char(port, sts, MAX310X_LSR_RXOVR_BIT, + one->rx_buf[rxlen-1], flag); + + } else { + if (unlikely(rxlen >= port->fifosize)) { + dev_warn_ratelimited(port->dev, "Possible RX FIFO overrun\n"); + port->icount.buf_overrun++; + printk("Possible RX FIFO overrun (%d)\n", port->icount.buf_overrun); + /* Ensure sanity of RX level */ + rxlen = port->fifosize; + } + + while (rxlen--) { + ch = max310x_port_read(port, MAX310X_RHR_REG); + sts = max310x_port_read(port, MAX310X_LSR_IRQSTS_REG); + + sts &= MAX310X_LSR_RXPAR_BIT | MAX310X_LSR_FRERR_BIT | + MAX310X_LSR_RXOVR_BIT | MAX310X_LSR_RXBRK_BIT; + + port->icount.rx++; + flag = TTY_NORMAL; + + if (unlikely(sts)) { + if (sts & MAX310X_LSR_RXBRK_BIT) { + port->icount.brk++; + if (uart_handle_break(port)) + continue; + } else if (sts & MAX310X_LSR_RXPAR_BIT) + port->icount.parity++; + else if (sts & MAX310X_LSR_FRERR_BIT) + port->icount.frame++; + else if (sts & MAX310X_LSR_RXOVR_BIT) + port->icount.overrun++; + + sts &= port->read_status_mask; + if (sts & MAX310X_LSR_RXBRK_BIT) + flag = TTY_BREAK; + else if (sts & MAX310X_LSR_RXPAR_BIT) + flag = TTY_PARITY; + else if (sts & MAX310X_LSR_FRERR_BIT) + flag = TTY_FRAME; + else if (sts & MAX310X_LSR_RXOVR_BIT) + flag = TTY_OVERRUN; + } + + if (uart_handle_sysrq_char(port, ch)) + continue; + + if (sts & port->ignore_status_mask) + continue; + + uart_insert_char(port, sts, MAX310X_LSR_RXOVR_BIT, ch, flag); + } + } + + tty_flip_buffer_push(&port->state->port); + // printk("handle rx end recv: %d\n", total_recv); +} + +static void max310x_handle_tx(struct uart_port *port) +{ + struct circ_buf *xmit = &port->state->xmit; + unsigned int txlen, to_send, until_end; + + if (unlikely(port->x_char)) { + max310x_port_write(port, MAX310X_THR_REG, port->x_char); + port->icount.tx++; + port->x_char = 0; + return; + } + + if (uart_circ_empty(xmit) || uart_tx_stopped(port)) + return; + + /* Get length of data pending in circular buffer */ + to_send = uart_circ_chars_pending(xmit); + until_end = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE); + if (likely(to_send)) { + /* Limit to size of TX FIFO */ + txlen = max310x_port_read(port, MAX310X_TXFIFOLVL_REG); + txlen = port->fifosize - txlen; + to_send = (to_send > txlen) ? txlen : to_send; + + if (until_end < to_send) { + /* It's a circ buffer -- wrap around. + * We could do that in one SPI transaction, but meh. */ + max310x_batch_write(port, xmit->buf + xmit->tail, until_end); + max310x_batch_write(port, xmit->buf, to_send - until_end); + } else { + max310x_batch_write(port, xmit->buf + xmit->tail, to_send); + } + + /* Add data to send */ + port->icount.tx += to_send; + xmit->tail = (xmit->tail + to_send) & (UART_XMIT_SIZE - 1); + } + + if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) + uart_write_wakeup(port); +} + +static void max310x_start_tx(struct uart_port *port) +{ + struct max310x_one *one = to_max310x_port(port); + // unsigned int ists; + // ists = max310x_port_read(port, MAX310X_IRQSTS_REG); + // printk("start tx ists: %x\n", ists); + schedule_work(&one->tx_work); +} + +static irqreturn_t max310x_port_irq(struct max310x_port *s, int portno) +{ + struct uart_port *port = &s->p[portno].port; + irqreturn_t res = IRQ_NONE; + + // unsigned int global_irq; + // global_irq = max310x_port_read(port, MAX310X_REG_1F); + // printk("Global IRQ STS check: %x\n", global_irq); + + do { + unsigned int ists, lsr, rxlen; + + /* Read IRQ status & RX FIFO level */ + ists = max310x_port_read(port, MAX310X_IRQSTS_REG); + rxlen = max310x_port_read(port, MAX310X_RXFIFOLVL_REG); + if (!ists && !rxlen) + { + + //printk("ists(%d)&&rxlen(%d)\n", ists, rxlen); + // int i=0; + // for(i; i<=0x1f; i++) + // printk("REG(%02x): %x\n", i, max310x_port_read(port, i)); + + + // printk("ISTS: %x\n", max310x_port_read(port, 0x2)); + // printk("MAX310X_LSR_IRQSTS_REG: %x\n", max310x_port_read(port, MAX310X_LSR_IRQSTS_REG)); + // printk("MAX310X_SPCHR_IRQSTS_REG: %x\n", max310x_port_read(port, MAX310X_SPCHR_IRQSTS_REG)); + // printk("MAX310X_STS_IRQSTS_REG: %x\n", max310x_port_read(port, MAX310X_STS_IRQSTS_REG)); + + // printk("RXLEN: %d\n", max310x_port_read(port, 0x12)); + + break; + } + // else{ + // printk("ists(%d)&&rxlen(%d)\n", ists, rxlen); + // int i=0; + // for(i; i<=0x1f; i++) + // printk("REG(%02x): %x\n", i, max310x_port_read(port, i)); + // } + + res = IRQ_HANDLED; + + if (ists & MAX310X_IRQ_CTS_BIT) { + printk("MAX310X_IRQ_CTS_BIT\n"); + lsr = max310x_port_read(port, MAX310X_LSR_IRQSTS_REG); + uart_handle_cts_change(port, + !!(lsr & MAX310X_LSR_CTS_BIT)); + } + if (rxlen) + { + // printk("ists: %x, rxlen: %d, handle rx\n", ists, rxlen); + max310x_handle_rx(port, rxlen); + } + if (ists & MAX310X_IRQ_TXEMPTY_BIT) + { + //printk("MAX310X_IRQ_TXEMPTY_BIT, start tx\n"); + max310x_start_tx(port); + } + } while (1); + return res; +} + +static irqreturn_t max310x_ist(int irq, void *dev_id) +{ + struct max310x_port *s = (struct max310x_port *)dev_id; + bool handled = false; + + unsigned int port_num; + if (s->devtype->nr > 1) { + do { + unsigned int val = ~0; + + // (regmap_read(s->regmap, MAX310X_GLOBALIRQ_REG, &val)); + WARN_ON_ONCE(regmap_read(s->regmap, + MAX310X_GLOBALIRQ_REG, &val)); + val = ((1 << s->devtype->nr) - 1) & ~val; + port_num = val; + + if (!val){ + //printk("port number invalid (%d), nr: %d isr break\n",val, s->devtype->nr); + handled = false; + break; + } + + if (max310x_port_irq(s, fls(val) - 1) == IRQ_HANDLED) + { + //printk("port number valid (%d), nr: %d isr handled \n",val, s->devtype->nr); + handled = true; + } + } while (1); + } else { + if (max310x_port_irq(s, 0) == IRQ_HANDLED) + { + // printk("port 0? probe action?\n"); + handled = true; + } + } + // printk("max310x_ist(%d) handled is %d\n", port_num, handled); + return IRQ_RETVAL(handled); +} + +static void max310x_tx_proc(struct work_struct *ws) +{ + struct max310x_one *one = container_of(ws, struct max310x_one, tx_work); + + max310x_handle_tx(&one->port); +} + +static unsigned int max310x_tx_empty(struct uart_port *port) +{ + u8 lvl = max310x_port_read(port, MAX310X_TXFIFOLVL_REG); + + return lvl ? 0 : TIOCSER_TEMT; +} + +static unsigned int max310x_get_mctrl(struct uart_port *port) +{ + /* DCD and DSR are not wired and CTS/RTS is handled automatically + * so just indicate DSR and CAR asserted + */ + return TIOCM_DSR | TIOCM_CAR; +} + +static void max310x_md_proc(struct work_struct *ws) +{ + struct max310x_one *one = container_of(ws, struct max310x_one, md_work); + + max310x_port_update(&one->port, MAX310X_MODE2_REG, + MAX310X_MODE2_LOOPBACK_BIT, + (one->port.mctrl & TIOCM_LOOP) ? + MAX310X_MODE2_LOOPBACK_BIT : 0); +} + +static void max310x_set_mctrl(struct uart_port *port, unsigned int mctrl) +{ + struct max310x_one *one = to_max310x_port(port); + + schedule_work(&one->md_work); +} + +static void max310x_break_ctl(struct uart_port *port, int break_state) +{ + max310x_port_update(port, MAX310X_LCR_REG, + MAX310X_LCR_TXBREAK_BIT, + break_state ? MAX310X_LCR_TXBREAK_BIT : 0); +} + +static void max310x_set_termios(struct uart_port *port, + struct ktermios *termios, + struct ktermios *old) +{ + unsigned int lcr = 0, flow = 0; + int baud; + + /* Mask termios capabilities we don't support */ + termios->c_cflag &= ~CMSPAR; + + /* Word size */ + switch (termios->c_cflag & CSIZE) { + case CS5: + break; + case CS6: + lcr = MAX310X_LCR_LENGTH0_BIT; + break; + case CS7: + lcr = MAX310X_LCR_LENGTH1_BIT; + break; + case CS8: + default: + lcr = MAX310X_LCR_LENGTH1_BIT | MAX310X_LCR_LENGTH0_BIT; + break; + } + + /* Parity */ + if (termios->c_cflag & PARENB) { + lcr |= MAX310X_LCR_PARITY_BIT; + if (!(termios->c_cflag & PARODD)) + lcr |= MAX310X_LCR_EVENPARITY_BIT; + } + + /* Stop bits */ + if (termios->c_cflag & CSTOPB) + lcr |= MAX310X_LCR_STOPLEN_BIT; /* 2 stops */ + + /* Update LCR register */ + max310x_port_write(port, MAX310X_LCR_REG, lcr); + + /* Set read status mask */ + port->read_status_mask = MAX310X_LSR_RXOVR_BIT; + if (termios->c_iflag & INPCK) + port->read_status_mask |= MAX310X_LSR_RXPAR_BIT | + MAX310X_LSR_FRERR_BIT; + if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK)) + port->read_status_mask |= MAX310X_LSR_RXBRK_BIT; + + /* Set status ignore mask */ + port->ignore_status_mask = 0; + if (termios->c_iflag & IGNBRK) + port->ignore_status_mask |= MAX310X_LSR_RXBRK_BIT; + if (!(termios->c_cflag & CREAD)) + port->ignore_status_mask |= MAX310X_LSR_RXPAR_BIT | + MAX310X_LSR_RXOVR_BIT | + MAX310X_LSR_FRERR_BIT | + MAX310X_LSR_RXBRK_BIT; + + /* Configure flow control */ + max310x_port_write(port, MAX310X_XON1_REG, termios->c_cc[VSTART]); + max310x_port_write(port, MAX310X_XOFF1_REG, termios->c_cc[VSTOP]); + + /* Disable transmitter before enabling AutoCTS or auto transmitter + * flow control + */ + if (termios->c_cflag & CRTSCTS || termios->c_iflag & IXOFF) { + max310x_port_update(port, MAX310X_MODE1_REG, + MAX310X_MODE1_TXDIS_BIT, + MAX310X_MODE1_TXDIS_BIT); + } + + port->status &= ~(UPSTAT_AUTOCTS | UPSTAT_AUTORTS | UPSTAT_AUTOXOFF); + + if (termios->c_cflag & CRTSCTS) { + /* Enable AUTORTS and AUTOCTS */ + port->status |= UPSTAT_AUTOCTS | UPSTAT_AUTORTS; + flow |= MAX310X_FLOWCTRL_AUTOCTS_BIT | + MAX310X_FLOWCTRL_AUTORTS_BIT; + } + if (termios->c_iflag & IXON) + flow |= MAX310X_FLOWCTRL_SWFLOW3_BIT | + MAX310X_FLOWCTRL_SWFLOWEN_BIT; + if (termios->c_iflag & IXOFF) { + port->status |= UPSTAT_AUTOXOFF; + flow |= MAX310X_FLOWCTRL_SWFLOW1_BIT | + MAX310X_FLOWCTRL_SWFLOWEN_BIT; + } + max310x_port_write(port, MAX310X_FLOWCTRL_REG, flow); + + /* Enable transmitter after disabling AutoCTS and auto transmitter + * flow control + */ + if (!(termios->c_cflag & CRTSCTS) && !(termios->c_iflag & IXOFF)) { + max310x_port_update(port, MAX310X_MODE1_REG, + MAX310X_MODE1_TXDIS_BIT, + 0); + } + + /* Get baud rate generator configuration */ + baud = uart_get_baud_rate(port, termios, old, + port->uartclk / 16 / 0xffff, + port->uartclk / 4); + + /* Setup baudrate generator */ + baud = max310x_set_baud(port, baud); + + /* Update timeout according to new baud rate */ + uart_update_timeout(port, termios->c_cflag, baud); +} + +static void max310x_rs_proc(struct work_struct *ws) +{ + struct max310x_one *one = container_of(ws, struct max310x_one, rs_work); + unsigned int delay, mode1 = 0, mode2 = 0; + + delay = (one->port.rs485.delay_rts_before_send << 4) | + one->port.rs485.delay_rts_after_send; + max310x_port_write(&one->port, MAX310X_HDPIXDELAY_REG, delay); + + if (one->port.rs485.flags & SER_RS485_ENABLED) { + mode1 = MAX310X_MODE1_TRNSCVCTRL_BIT; + + if (!(one->port.rs485.flags & SER_RS485_RX_DURING_TX)) + mode2 = MAX310X_MODE2_ECHOSUPR_BIT; + } + + max310x_port_update(&one->port, MAX310X_MODE1_REG, + MAX310X_MODE1_TRNSCVCTRL_BIT, mode1); + max310x_port_update(&one->port, MAX310X_MODE2_REG, + MAX310X_MODE2_ECHOSUPR_BIT, mode2); +} + +static int max310x_rs485_config(struct uart_port *port, + struct serial_rs485 *rs485) +{ + struct max310x_one *one = to_max310x_port(port); + + if ((rs485->delay_rts_before_send > 0x0f) || + (rs485->delay_rts_after_send > 0x0f)) + return -ERANGE; + + rs485->flags &= SER_RS485_RTS_ON_SEND | SER_RS485_RX_DURING_TX | + SER_RS485_ENABLED; + memset(rs485->padding, 0, sizeof(rs485->padding)); + port->rs485 = *rs485; + + schedule_work(&one->rs_work); + + return 0; +} + + +static int max310x_startup(struct uart_port *port) +{ + + printk("max3109 startup\n"); + struct max310x_port *s = dev_get_drvdata(port->dev); + unsigned int val; + + s->devtype->power(port, 1); + + /* Configure MODE1 register */ + max310x_port_update(port, MAX310X_MODE1_REG, + MAX310X_MODE1_TRNSCVCTRL_BIT, 0); + + /* Configure MODE2 register & Reset FIFOs*/ + val = MAX310X_MODE2_RXEMPTINV_BIT | MAX310X_MODE2_FIFORST_BIT; + max310x_port_write(port, MAX310X_MODE2_REG, val); + max310x_port_update(port, MAX310X_MODE2_REG, + MAX310X_MODE2_FIFORST_BIT, 0); + + /* Configure mode1/mode2 to have rs485/rs232 enabled at startup */ + val = (clamp(port->rs485.delay_rts_before_send, 0U, 15U) << 4) | + clamp(port->rs485.delay_rts_after_send, 0U, 15U); + max310x_port_write(port, MAX310X_HDPIXDELAY_REG, val); + + if (port->rs485.flags & SER_RS485_ENABLED) { + printk("SER_RS485_Enable\n"); + max310x_port_update(port, MAX310X_MODE1_REG, + MAX310X_MODE1_TRNSCVCTRL_BIT, + MAX310X_MODE1_TRNSCVCTRL_BIT); + + if (!(port->rs485.flags & SER_RS485_RX_DURING_TX)){ + printk("SER_RS485_RX_DURING_TX\n"); + max310x_port_update(port, MAX310X_MODE2_REG, + MAX310X_MODE2_ECHOSUPR_BIT, + MAX310X_MODE2_ECHOSUPR_BIT); + } + } + + /* Configure flow control levels */ + /* Flow control halt level 96, resume level 48 */ + max310x_port_write(port, MAX310X_FLOWLVL_REG, + MAX310X_FLOWLVL_RES(48) | MAX310X_FLOWLVL_HALT(96)); + + /* Clear IRQ status register */ + max310x_port_read(port, MAX310X_IRQSTS_REG); + + /* Enable RX, TX, CTS change interrupts */ + val = MAX310X_IRQ_RXEMPTY_BIT | MAX310X_IRQ_TXEMPTY_BIT; + max310x_port_write(port, MAX310X_IRQEN_REG, val | MAX310X_IRQ_CTS_BIT); + + return 0; +} + +static void max310x_shutdown(struct uart_port *port) +{ + printk("max310x shutdown\n"); + struct max310x_port *s = dev_get_drvdata(port->dev); + + /* Disable all interrupts */ + max310x_port_write(port, MAX310X_IRQEN_REG, 0); + + s->devtype->power(port, 0); +} + +static const char *max310x_type(struct uart_port *port) +{ + struct max310x_port *s = dev_get_drvdata(port->dev); + + return (port->type == PORT_MAX310X) ? s->devtype->name : NULL; +} + +static int max310x_request_port(struct uart_port *port) +{ + /* Do nothing */ + return 0; +} + +static void max310x_config_port(struct uart_port *port, int flags) +{ + if (flags & UART_CONFIG_TYPE) + port->type = PORT_MAX310X; +} + +static int max310x_verify_port(struct uart_port *port, struct serial_struct *s) +{ + if ((s->type != PORT_UNKNOWN) && (s->type != PORT_MAX310X)) + return -EINVAL; + if (s->irq != port->irq) + return -EINVAL; + + return 0; +} + +static void max310x_null_void(struct uart_port *port) +{ + /* Do nothing */ +} + +static const struct uart_ops max310x_ops = { + .tx_empty = max310x_tx_empty, + .set_mctrl = max310x_set_mctrl, + .get_mctrl = max310x_get_mctrl, + .stop_tx = max310x_null_void, + .start_tx = max310x_start_tx, + .stop_rx = max310x_null_void, + .break_ctl = max310x_break_ctl, + .startup = max310x_startup, + .shutdown = max310x_shutdown, + .set_termios = max310x_set_termios, + .type = max310x_type, + .request_port = max310x_request_port, + .release_port = max310x_null_void, + .config_port = max310x_config_port, + .verify_port = max310x_verify_port, +}; + +static int __maybe_unused max310x_suspend(struct device *dev) +{ + struct max310x_port *s = dev_get_drvdata(dev); + int i; + + for (i = 0; i < s->devtype->nr; i++) { + uart_suspend_port(&max310x_uart, &s->p[i].port); + s->devtype->power(&s->p[i].port, 0); + } + + return 0; +} + +static int __maybe_unused max310x_resume(struct device *dev) +{ + struct max310x_port *s = dev_get_drvdata(dev); + int i; + + for (i = 0; i < s->devtype->nr; i++) { + s->devtype->power(&s->p[i].port, 1); + uart_resume_port(&max310x_uart, &s->p[i].port); + } + + return 0; +} + +static SIMPLE_DEV_PM_OPS(max310x_pm_ops, max310x_suspend, max310x_resume); + +#ifdef CONFIG_GPIOLIB +static int max310x_gpio_get(struct gpio_chip *chip, unsigned offset) +{ + unsigned int val; + struct max310x_port *s = gpiochip_get_data(chip); + struct uart_port *port = &s->p[offset / 4].port; + + val = max310x_port_read(port, MAX310X_GPIODATA_REG); + + return !!((val >> 4) & (1 << (offset % 4))); +} + +static void max310x_gpio_set(struct gpio_chip *chip, unsigned offset, int value) +{ + struct max310x_port *s = gpiochip_get_data(chip); + struct uart_port *port = &s->p[offset / 4].port; + + max310x_port_update(port, MAX310X_GPIODATA_REG, 1 << (offset % 4), + value ? 1 << (offset % 4) : 0); +} + +static int max310x_gpio_direction_input(struct gpio_chip *chip, unsigned offset) +{ + struct max310x_port *s = gpiochip_get_data(chip); + struct uart_port *port = &s->p[offset / 4].port; + + max310x_port_update(port, MAX310X_GPIOCFG_REG, 1 << (offset % 4), 0); + + return 0; +} + +static int max310x_gpio_direction_output(struct gpio_chip *chip, + unsigned offset, int value) +{ + struct max310x_port *s = gpiochip_get_data(chip); + struct uart_port *port = &s->p[offset / 4].port; + + max310x_port_update(port, MAX310X_GPIODATA_REG, 1 << (offset % 4), + value ? 1 << (offset % 4) : 0); + max310x_port_update(port, MAX310X_GPIOCFG_REG, 1 << (offset % 4), + 1 << (offset % 4)); + + return 0; +} + +static int max310x_gpio_set_config(struct gpio_chip *chip, unsigned int offset, + unsigned long config) +{ + struct max310x_port *s = gpiochip_get_data(chip); + struct uart_port *port = &s->p[offset / 4].port; + + switch (pinconf_to_config_param(config)) { + case PIN_CONFIG_DRIVE_OPEN_DRAIN: + max310x_port_update(port, MAX310X_GPIOCFG_REG, + 1 << ((offset % 4) + 4), + 1 << ((offset % 4) + 4)); + return 0; + case PIN_CONFIG_DRIVE_PUSH_PULL: + max310x_port_update(port, MAX310X_GPIOCFG_REG, + 1 << ((offset % 4) + 4), 0); + return 0; + default: + return -ENOTSUPP; + } +} +#endif + +static int max310x_probe(struct device *dev, struct max310x_devtype *devtype, + struct regmap *regmap, int irq) +{ + int i, ret, fmin, fmax, freq, uartclk; + struct clk *clk_osc, *clk_xtal, *clk_null; + struct max310x_port *s; + bool xtal = false; + + if (IS_ERR(regmap)) + return PTR_ERR(regmap); + + /* Alloc port structure */ + s = devm_kzalloc(dev, struct_size(s, p, devtype->nr), GFP_KERNEL); + if (!s) { + dev_err(dev, "Error allocating port structure\n"); + return -ENOMEM; + } + + clk_osc = devm_clk_get(dev, "osc"); + clk_xtal = devm_clk_get(dev, "xtal"); + clk_null = devm_clk_get(dev, NULL); + + printk("clk_osc = %p, iserr: %d\n", clk_osc, IS_ERR(clk_osc)); + printk("clk_xtal = %p, iserr: %d\n", clk_xtal, IS_ERR(clk_xtal)); + printk("clk_null = %p, iserr: %d\n", clk_null, IS_ERR(clk_null)); + + + + + if (!IS_ERR(clk_osc)) { + s->clk = clk_osc; + fmin = 500000; + fmax = 35000000; + } + else if (!IS_ERR(clk_null)) { + s->clk = clk_null; + fmin = 500000; + fmax = 35000000; + printk("clk null rate: %ld\n", clk_get_rate(clk_null)); + } else if (!IS_ERR(clk_xtal)) { + s->clk = clk_xtal; + fmin = 1000000; + fmax = 4000000; + xtal = true; + } else if (PTR_ERR(clk_osc) == -EPROBE_DEFER || + PTR_ERR(clk_xtal) == -EPROBE_DEFER) { + return -EPROBE_DEFER; + } else { + dev_err(dev, "Cannot get clock\n"); + return -EINVAL; + } + + ret = clk_prepare_enable(s->clk); + if (ret) + return ret; + + freq = clk_get_rate(s->clk); + /* Check frequency limits */ + if (freq < fmin || freq > fmax) { + ret = -ERANGE; + goto out_clk; + } + + s->regmap = regmap; + s->devtype = devtype; + dev_set_drvdata(dev, s); + + /* Check device to ensure we are talking to what we expect */ + ret = devtype->detect(dev); + if (ret) + goto out_clk; + + for (i = 0; i < devtype->nr; i++) { + unsigned int offs = i << 5; + + /* Reset port */ + regmap_write(s->regmap, MAX310X_MODE2_REG + offs, + MAX310X_MODE2_RST_BIT); + /* Clear port reset */ + regmap_write(s->regmap, MAX310X_MODE2_REG + offs, 0); + + /* Wait for port startup */ + do { + regmap_read(s->regmap, + MAX310X_BRGDIVLSB_REG + offs, &ret); + } while (ret != 0x01); + + regmap_write(s->regmap, MAX310X_MODE1_REG + offs, + devtype->mode1); + } + + uartclk = max310x_set_ref_clk(dev, s, freq, xtal); + dev_dbg(dev, "Reference clock set to %i Hz\n", uartclk); + printk("Reference clock set to %i Hz\n", uartclk); + + for (i = 0; i < devtype->nr; i++) { + unsigned int line; + + line = find_first_zero_bit(max310x_lines, MAX310X_UART_NRMAX); + if (line == MAX310X_UART_NRMAX) { + ret = -ERANGE; + goto out_uart; + } + + /* Initialize port data */ + s->p[i].port.line = line; + s->p[i].port.dev = dev; + s->p[i].port.irq = irq; + s->p[i].port.type = PORT_MAX310X; + s->p[i].port.fifosize = MAX310X_FIFO_SIZE; + s->p[i].port.flags = UPF_FIXED_TYPE | UPF_LOW_LATENCY; + s->p[i].port.iotype = UPIO_PORT; + s->p[i].port.iobase = i * 0x20; + s->p[i].port.membase = (void __iomem *)~0; + s->p[i].port.uartclk = uartclk; + s->p[i].port.rs485_config = max310x_rs485_config; + s->p[i].port.ops = &max310x_ops; + /* Disable all interrupts */ + max310x_port_write(&s->p[i].port, MAX310X_IRQEN_REG, 0); + /* Clear IRQ status register */ + max310x_port_read(&s->p[i].port, MAX310X_IRQSTS_REG); + /* Initialize queue for start TX */ + INIT_WORK(&s->p[i].tx_work, max310x_tx_proc); + /* Initialize queue for changing LOOPBACK mode */ + INIT_WORK(&s->p[i].md_work, max310x_md_proc); + /* Initialize queue for changing RS485 mode */ + INIT_WORK(&s->p[i].rs_work, max310x_rs_proc); + /* Initialize SPI-transfer buffers */ + s->p[i].wr_header = (s->p[i].port.iobase + MAX310X_THR_REG) | + MAX310X_WRITE_BIT; + s->p[i].rd_header = (s->p[i].port.iobase + MAX310X_RHR_REG); + + /* Register port */ + ret = uart_add_one_port(&max310x_uart, &s->p[i].port); + if (ret) { + s->p[i].port.dev = NULL; + goto out_uart; + } + set_bit(line, max310x_lines); + + /* Go to suspend mode */ + devtype->power(&s->p[i].port, 0); + } + +#ifdef CONFIG_GPIOLIB + /* Setup GPIO cotroller */ + s->gpio.owner = THIS_MODULE; + s->gpio.parent = dev; + s->gpio.label = devtype->name; + s->gpio.direction_input = max310x_gpio_direction_input; + s->gpio.get = max310x_gpio_get; + s->gpio.direction_output= max310x_gpio_direction_output; + s->gpio.set = max310x_gpio_set; + s->gpio.set_config = max310x_gpio_set_config; + s->gpio.base = -1; + s->gpio.ngpio = devtype->nr * 4; + s->gpio.can_sleep = 1; + ret = devm_gpiochip_add_data(dev, &s->gpio, s); + if (ret) + goto out_uart; +#endif + + /* Setup interrupt */ + ret = devm_request_threaded_irq(dev, irq, NULL, max310x_ist, + IRQF_ONESHOT | IRQF_SHARED, dev_name(dev), s); + if (!ret) + return 0; + + dev_err(dev, "Unable to reguest IRQ %i\n", irq); + +out_uart: + for (i = 0; i < devtype->nr; i++) { + if (s->p[i].port.dev) { + uart_remove_one_port(&max310x_uart, &s->p[i].port); + clear_bit(s->p[i].port.line, max310x_lines); + } + } + +out_clk: + clk_disable_unprepare(s->clk); + + return ret; +} + +static int max310x_remove(struct device *dev) +{ + struct max310x_port *s = dev_get_drvdata(dev); + int i; + + for (i = 0; i < s->devtype->nr; i++) { + cancel_work_sync(&s->p[i].tx_work); + cancel_work_sync(&s->p[i].md_work); + cancel_work_sync(&s->p[i].rs_work); + uart_remove_one_port(&max310x_uart, &s->p[i].port); + clear_bit(s->p[i].port.line, max310x_lines); + s->devtype->power(&s->p[i].port, 0); + } + + clk_disable_unprepare(s->clk); + printk("max3109 remove\n"); + + return 0; +} + +static const struct of_device_id __maybe_unused max310x_dt_ids[] = { + { .compatible = "maxim,max3107", .data = &max3107_devtype, }, + { .compatible = "maxim,max3108", .data = &max3108_devtype, }, + { .compatible = "maxim,max3109", .data = &max3109_devtype, }, + { .compatible = "maxim,max14830", .data = &max14830_devtype }, + { } +}; +MODULE_DEVICE_TABLE(of, max310x_dt_ids); + +static struct regmap_config regcfg = { + .reg_bits = 8, + .val_bits = 8, + .write_flag_mask = MAX310X_WRITE_BIT, + .cache_type = REGCACHE_RBTREE, + .writeable_reg = max310x_reg_writeable, + .volatile_reg = max310x_reg_volatile, + .precious_reg = max310x_reg_precious, +}; + +#ifdef CONFIG_SPI_MASTER +static int max310x_spi_probe(struct spi_device *spi) +{ + struct max310x_devtype *devtype; + struct regmap *regmap; + int ret; + + /* Setup SPI bus */ + spi->bits_per_word = 8; + spi->mode = spi->mode ? : SPI_MODE_0; + spi->max_speed_hz = spi->max_speed_hz ? : 26000000; + ret = spi_setup(spi); + if (ret) + return ret; + + if (spi->dev.of_node) { + const struct of_device_id *of_id = + of_match_device(max310x_dt_ids, &spi->dev); + if (!of_id) + return -ENODEV; + + devtype = (struct max310x_devtype *)of_id->data; + } else { + const struct spi_device_id *id_entry = spi_get_device_id(spi); + + devtype = (struct max310x_devtype *)id_entry->driver_data; + } + + regcfg.max_register = devtype->nr * 0x20 - 1; + regmap = devm_regmap_init_spi(spi, ®cfg); + + return max310x_probe(&spi->dev, devtype, regmap, spi->irq); +} + +static int max310x_spi_remove(struct spi_device *spi) +{ + return max310x_remove(&spi->dev); +} + +static const struct spi_device_id max310x_id_table[] = { + { "max3107", (kernel_ulong_t)&max3107_devtype, }, + { "max3108", (kernel_ulong_t)&max3108_devtype, }, + { "max3109", (kernel_ulong_t)&max3109_devtype, }, + { "max14830", (kernel_ulong_t)&max14830_devtype, }, + { } +}; +MODULE_DEVICE_TABLE(spi, max310x_id_table); + +static struct spi_driver max310x_spi_driver = { + .driver = { + .name = MAX310X_NAME, + .of_match_table = of_match_ptr(max310x_dt_ids), + .pm = &max310x_pm_ops, + }, + .probe = max310x_spi_probe, + .remove = max310x_spi_remove, + .id_table = max310x_id_table, +}; +#endif + +static int __init max310x_uart_init(void) +{ + int ret; + printk("max3109_uart_init - test\n"); + printk("max310x_spi_driver\n"); + /* Register UART driver */ + printk("max310x_spi_driver name: %s\n", max310x_spi_driver.driver.name); + printk("max310x_spi_driver id_table: %s\n", max310x_spi_driver.id_table[0].name); + printk("max310x_spi_driver id_table: %d\n", max310x_spi_driver.id_table[0].driver_data); + + printk("uart_register_driver\n"); + printk("max310x_uart name: %s\n", max310x_uart.driver_name); + printk("max310x_uart nr: %d\n", max310x_uart.nr); + printk("max310x_uart dev_name: %s\n", max310x_uart.dev_name); + printk("max310x_uart major: %d\n", max310x_uart.major); + printk("max310x_uart minor: %d\n", max310x_uart.minor); + + bitmap_zero(max310x_lines, MAX310X_UART_NRMAX); + + ret = uart_register_driver(&max310x_uart); + printk("uart register driver ret: %d\n", ret); + if (ret) + return ret; + +#ifdef CONFIG_SPI_MASTER + ret = spi_register_driver(&max310x_spi_driver); + printk("spi register driver ret: %d\n", ret); +#endif + + return ret; +} +module_init(max310x_uart_init); + +static void __exit max310x_uart_exit(void) +{ +#ifdef CONFIG_SPI_MASTER + spi_unregister_driver(&max310x_spi_driver); +#endif + + uart_unregister_driver(&max310x_uart); +} +module_exit(max310x_uart_exit); + +MODULE_LICENSE("GPL"); +MODULE_AUTHOR("Alexander Shiyan "); +MODULE_DESCRIPTION("MAX310X serial driver"); diff --git a/meta-st/meta-st-stm32mpu-hce/recipes-kernel/max3109-test/max3109-test.bb b/meta-st/meta-st-stm32mpu-hce/recipes-kernel/max3109-test/max3109-test.bb new file mode 100644 index 0000000..52c9623 --- /dev/null +++ b/meta-st/meta-st-stm32mpu-hce/recipes-kernel/max3109-test/max3109-test.bb @@ -0,0 +1,18 @@ +# +# Yocto recipe to build a kernel module out of the kernel tree +# hello-module.bb +# www.makersweb.net +# + +DESCRIPTION = "MAX3109 Test kernel module out of the kernel tree" +SECTION = "examples" +LICENSE = "CLOSED" +PR = "r0" + +inherit module + +SRC_URI = "file://max3109test.c \ + file://Makefile \ + " + +S = "${WORKDIR}" \ No newline at end of file diff --git a/meta-st/meta-st-stm32mpu-hce/recipes-kernel/tlc59108-test/files/Makefile b/meta-st/meta-st-stm32mpu-hce/recipes-kernel/tlc59108-test/files/Makefile new file mode 100644 index 0000000..8c0cac2 --- /dev/null +++ b/meta-st/meta-st-stm32mpu-hce/recipes-kernel/tlc59108-test/files/Makefile @@ -0,0 +1,16 @@ +obj-m += tlc591xx.o + +SRC := $(shell pwd) + +all: + $(MAKE) -C $(KERNEL_SRC) M=$(SRC) modules + +modules_install: + $(MAKE) -C $(KERNEL_SRC) M=$(SRC) modules_install +kernel_clean: + $(MAKE) -C $(KERNEL_SRC) M=$(PWD) clean + +clean: kernel_clean + rm -rf Module.symvers modules.order +# clean: +# rm *.o \ No newline at end of file diff --git a/meta-st/meta-st-stm32mpu-hce/recipes-kernel/tlc59108-test/files/tlc591xx.c b/meta-st/meta-st-stm32mpu-hce/recipes-kernel/tlc59108-test/files/tlc591xx.c new file mode 100644 index 0000000..a2182a4 --- /dev/null +++ b/meta-st/meta-st-stm32mpu-hce/recipes-kernel/tlc59108-test/files/tlc591xx.c @@ -0,0 +1,296 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright 2014 Belkin Inc. + * Copyright 2015 Andrew Lunn + */ + +#include +#include +#include +#include +#include +#include +#include + +#define TLC591XX_MAX_LEDS 16 + +#define TLC591XX_REG_MODE1 0x00 +#define MODE1_RESPON_ADDR_MASK 0xF0 +#define MODE1_NORMAL_MODE (0 << 4) +#define MODE1_SPEED_MODE (1 << 4) + +#define TLC591XX_REG_MODE2 0x01 +#define MODE2_DIM (0 << 5) +#define MODE2_BLINK (1 << 5) +#define MODE2_OCH_STOP (0 << 3) +#define MODE2_OCH_ACK (1 << 3) + +#define TLC591XX_REG_PWM(x) (0x02 + (x)) + +#define TLC591XX_REG_GRPPWM 0x12 +#define TLC591XX_REG_GRPFREQ 0x13 + +/* LED Driver Output State, determine the source that drives LED outputs */ +#define LEDOUT_OFF 0x0 /* Output LOW */ +#define LEDOUT_ON 0x1 /* Output HI-Z */ +#define LEDOUT_DIM 0x2 /* Dimming */ +#define LEDOUT_BLINK 0x3 /* Blinking */ +#define LEDOUT_MASK 0x3 + +#define ldev_to_led(c) container_of(c, struct tlc591xx_led, ldev) + +struct tlc591xx_led { + bool active; + unsigned int led_no; + struct led_classdev ldev; + struct tlc591xx_priv *priv; +}; + +struct tlc591xx_priv { + struct tlc591xx_led leds[TLC591XX_MAX_LEDS]; + struct regmap *regmap; + unsigned int reg_ledout_offset; +}; + +struct tlc591xx { + unsigned int max_leds; + unsigned int reg_ledout_offset; +}; + +static const struct tlc591xx tlc59116 = { + .max_leds = 16, + .reg_ledout_offset = 0x14, +}; + +static const struct tlc591xx tlc59108 = { + .max_leds = 8, + .reg_ledout_offset = 0x0c, +}; + +static int +tlc591xx_set_mode(struct regmap *regmap, u8 mode) +{ + int err; + u8 val; + + err = regmap_write(regmap, TLC591XX_REG_MODE1, MODE1_NORMAL_MODE); + if (err) + return err; + + val = MODE2_OCH_STOP | mode; + + return regmap_write(regmap, TLC591XX_REG_MODE2, val); +} + +static int +tlc591xx_set_ledout(struct tlc591xx_priv *priv, struct tlc591xx_led *led, + u8 val) +{ + unsigned int i = (led->led_no % 4) * 2; + unsigned int mask = LEDOUT_MASK << i; + unsigned int addr = priv->reg_ledout_offset + (led->led_no >> 2); + + val = val << i; + printk("tlc591xx_set_ledout. i: %d, mask: %d, addr: %d, val: %d\r\n", i, mask, addr, val ); + + return regmap_update_bits(priv->regmap, addr, mask, val); +} + +static int +tlc591xx_set_pwm(struct tlc591xx_priv *priv, struct tlc591xx_led *led, + u8 brightness) +{ + u8 pwm = TLC591XX_REG_PWM(led->led_no); + + return regmap_write(priv->regmap, pwm, brightness); +} + +static int +tlc591xx_brightness_set(struct led_classdev *led_cdev, + enum led_brightness brightness) +{ + struct tlc591xx_led *led = ldev_to_led(led_cdev); + struct tlc591xx_priv *priv = led->priv; + int err; + + switch (brightness) { + case 0: + err = tlc591xx_set_ledout(priv, led, LEDOUT_OFF); + break; + case LED_FULL: + err = tlc591xx_set_ledout(priv, led, LEDOUT_ON); + break; + default: + err = tlc591xx_set_ledout(priv, led, LEDOUT_DIM); + if (!err) + err = tlc591xx_set_pwm(priv, led, brightness); + } + + return err; +} + +static void +tlc591xx_destroy_devices(struct tlc591xx_priv *priv, unsigned int j) +{ + int i = j; + + while (--i >= 0) { + if (priv->leds[i].active) + led_classdev_unregister(&priv->leds[i].ldev); + } +} + +static int +tlc591xx_configure(struct device *dev, + struct tlc591xx_priv *priv, + const struct tlc591xx *tlc591xx) +{ + unsigned int i; + int err = 0; + + printk("tlc591xx_configure\r\n"); + tlc591xx_set_mode(priv->regmap, MODE2_DIM); + for (i = 0; i < TLC591XX_MAX_LEDS; i++) { + struct tlc591xx_led *led = &priv->leds[i]; + + if (!led->active) + continue; + + led->priv = priv; + led->led_no = i; + led->ldev.brightness_set_blocking = tlc591xx_brightness_set; + led->ldev.max_brightness = LED_FULL; + err = led_classdev_register(dev, &led->ldev); + if (err < 0) { + dev_err(dev, "couldn't register LED %s\n", + led->ldev.name); + goto exit; + } + } + printk("tlc591xx_configure ok\r\n"); + + return 0; + +exit: + tlc591xx_destroy_devices(priv, i); + return err; +} + +static const struct regmap_config tlc591xx_regmap = { + .reg_bits = 8, + .val_bits = 8, + .max_register = 0x1e, +}; + +static const struct of_device_id of_tlc591xx_leds_match[] = { + { .compatible = "ti,tlc59116", + .data = &tlc59116 }, + { .compatible = "ti,tlc59108", + .data = &tlc59108 }, + {}, +}; +MODULE_DEVICE_TABLE(of, of_tlc591xx_leds_match); + +static int +tlc591xx_probe(struct i2c_client *client, + const struct i2c_device_id *id) +{ + struct device_node *np = client->dev.of_node, *child; + struct device *dev = &client->dev; + const struct of_device_id *match; + const struct tlc591xx *tlc591xx; + struct tlc591xx_priv *priv; + int err, count, reg; + + printk("tlc591xx_probe\r\n"); + match = of_match_device(of_tlc591xx_leds_match, dev); + if (!match) + return -ENODEV; + printk("match\r\n"); + tlc591xx = match->data; + if (!np) + return -ENODEV; + printk("np ok\r\n"); + count = of_get_child_count(np); + if (!count || count > tlc591xx->max_leds) + return -EINVAL; + printk("count ok\r\n"); + priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + printk("priv ok\r\n"); + priv->regmap = devm_regmap_init_i2c(client, &tlc591xx_regmap); + if (IS_ERR(priv->regmap)) { + err = PTR_ERR(priv->regmap); + dev_err(dev, "Failed to allocate register map: %d\n", err); + return err; + } + priv->reg_ledout_offset = tlc591xx->reg_ledout_offset; + printk("priv->reg_ledout_offset: %d\r\n", priv->reg_ledout_offset); + i2c_set_clientdata(client, priv); + printk("i2c_set_clientdata\r\n"); + for_each_child_of_node(np, child) { + err = of_property_read_u32(child, "reg", ®); + printk("err:%d, reg:%d\r\n", err, reg); + // int i; + // for(i=0; i<0x14; i++) + // { + // // printk("i: %d\r\n", i); + // err = of_property_read_u32(child, "reg", &i); + // printk("err:%d, reg:%d\r\n", err, reg); + // i++; + // } + + if (err) { + of_node_put(child); + printk("err\r\n"); + return err; + } + if (reg < 0 || reg >= tlc591xx->max_leds || + priv->leds[reg].active) { + of_node_put(child); + printk("reg err? return EINVAL\r\n"); + // return -EINVAL; + } + priv->leds[reg].active = true; + priv->leds[reg].ldev.name = + of_get_property(child, "label", NULL) ? : child->name; + priv->leds[reg].ldev.default_trigger = + of_get_property(child, "linux,default-trigger", NULL); + } + printk("for_each_child_of_node\r\n"); + return tlc591xx_configure(dev, priv, tlc591xx); +} + +static int +tlc591xx_remove(struct i2c_client *client) +{ + struct tlc591xx_priv *priv = i2c_get_clientdata(client); + + tlc591xx_destroy_devices(priv, TLC591XX_MAX_LEDS); + + return 0; +} + +static const struct i2c_device_id tlc591xx_id[] = { + { "tlc59116" }, + { "tlc59108" }, + {}, +}; +MODULE_DEVICE_TABLE(i2c, tlc591xx_id); + +static struct i2c_driver tlc591xx_driver = { + .driver = { + .name = "tlc591xx", + .of_match_table = of_match_ptr(of_tlc591xx_leds_match), + }, + .probe = tlc591xx_probe, + .remove = tlc591xx_remove, + .id_table = tlc591xx_id, +}; + +module_i2c_driver(tlc591xx_driver); + +MODULE_AUTHOR("Andrew Lunn "); +MODULE_LICENSE("GPL"); +MODULE_DESCRIPTION("TLC591XX LED driver"); \ No newline at end of file diff --git a/meta-st/meta-st-stm32mpu-hce/recipes-kernel/tlc59108-test/tlc59108.bb b/meta-st/meta-st-stm32mpu-hce/recipes-kernel/tlc59108-test/tlc59108.bb new file mode 100644 index 0000000..d6b4361 --- /dev/null +++ b/meta-st/meta-st-stm32mpu-hce/recipes-kernel/tlc59108-test/tlc59108.bb @@ -0,0 +1,20 @@ +# +# Yocto recipe to build a kernel module out of the kernel tree +# hello-module.bb +# www.makersweb.net +# + +DESCRIPTION = "Hello kernel module out of the kernel tree" +SECTION = "examples" +LICENSE = "CLOSED" +#LICENSE = "GPLv2" +#LIC_FILES_CHKSUM = "file://COPYING;md5=12f884d2ae1ff87c09e5b7ccc2c4ca7e" +PR = "r0" + +inherit module + +SRC_URI = "file://tlc591xx.c \ + file://Makefile \ + " + +S = "${WORKDIR}" \ No newline at end of file diff --git a/meta-st/meta-st-stm32mpu-hce/recipes-st/images/st-image-hce.bb b/meta-st/meta-st-stm32mpu-hce/recipes-st/images/st-image-hce.bb new file mode 100644 index 0000000..076eb0e --- /dev/null +++ b/meta-st/meta-st-stm32mpu-hce/recipes-st/images/st-image-hce.bb @@ -0,0 +1,39 @@ +require recipes-st/images/st-image-weston.bb + +SUMMARY = "OpenSTLinux AWS greengrass image based on weston image" + +IMAGE_AWSGREENGRASS_PART = "\ + greengrass \ +" + + +# for greengrass certification testing with TPM +IMAGE_AWSGREENGRASSTEST_PART = "\ + greengrasstests \ + sudo \ +" + +# sqlite3 already in greengrass.inc RDEPENDS_${PN} +IMAGE_TPM2PKCS11_PART = " \ + tpm2-pkcs11 \ + tpm2-tss-engine \ + python3-pyyaml \ + python3-cryptography \ + python3-sqlite3 \ + python3-pip \ +" + +# +# INSTALL addons +# +CORE_IMAGE_EXTRA_INSTALL += " \ + ${IMAGE_AWSGREENGRASS_PART} \ + ${IMAGE_AWSGREENGRASSTEST_PART} \ + ${@bb.utils.contains('DISTRO_FEATURES', 'tpm2', '${IMAGE_TPM2PKCS11_PART}', '', d)}\ + openjdk-8 \ + python3 \ +" + +IMAGE_FEATURES += "\ + ${@bb.utils.contains('CORE_IMAGE_EXTRA_INSTALL', 'greengrasstests', 'ssh-server-openssh', '', d)}\ +" diff --git a/meta-st/meta-st-stm32mpu-hce/recipes-tpm2/tpm2-pkcs11/tpm2-pkcs11_%.bbappend b/meta-st/meta-st-stm32mpu-hce/recipes-tpm2/tpm2-pkcs11/tpm2-pkcs11_%.bbappend new file mode 100644 index 0000000..8e653d8 --- /dev/null +++ b/meta-st/meta-st-stm32mpu-hce/recipes-tpm2/tpm2-pkcs11/tpm2-pkcs11_%.bbappend @@ -0,0 +1,14 @@ +#Install tools script to initialise the PKC11/TPM2 (script python : ./tpm2_ptool.py) + +do_install_append() { + install -d ${D}/tools/tpm2_pkcs11 + install -m 755 ${S}/tools/*.py ${D}/tools + install -m 755 ${S}/tools/tpm2_ptool ${D}/tools + install -m 755 ${S}/tools/tpm2_pkcs11/* ${D}/tools/tpm2_pkcs11 +} + +FILES_${PN} += "/tools/*" +FILES_${PN} += "/tools/tpm2_pkcs11/*" + + + diff --git a/meta-st/scripts b/meta-st/scripts new file mode 160000 index 0000000..b600010 --- /dev/null +++ b/meta-st/scripts @@ -0,0 +1 @@ +Subproject commit b600010fa49e2bd4d3f10b732405200de974d3e2 diff --git a/meta-timesys b/meta-timesys new file mode 160000 index 0000000..83d534e --- /dev/null +++ b/meta-timesys @@ -0,0 +1 @@ +Subproject commit 83d534e4eaf54685e956b8a77b61a40b06ad42ec diff --git a/meta-virtualization b/meta-virtualization new file mode 160000 index 0000000..7588686 --- /dev/null +++ b/meta-virtualization @@ -0,0 +1 @@ +Subproject commit 758868633be479f38d19c3602be0094289fc1a75 diff --git a/openembedded-core b/openembedded-core new file mode 160000 index 0000000..1795f30 --- /dev/null +++ b/openembedded-core @@ -0,0 +1 @@ +Subproject commit 1795f30d8ab73d35710ca99064c51190dc84853e